85605-A-2 Sheet 1/8 — CPU (Z80)

manual p23 · 19 ICs · 19 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Interboard connectors (the band cables between the boards) — circled letter+number labels on the drawing are connector row + pin
11M — Z80A: Main CPU, 3MHz PHIMAIN. Data bus D0'-D7' runs through the custom decryptor (sheet 1/1) to the ROM/RAM D bus — verified 2026-07-21 11M ✓ Z80A $PHICPU · 3MHz PHIMAIN buffered through 8K (pin 3), 560R pullup PHI 6 $PHICPU D4' D4 7 D4' D3' D3 8 D3' D5' D5 9 D5' D6' D6 10 D6' D2' D2 12 D2' D7' D7 13 D7' D0' D0 14 D0' D1' D1 15 D1' $INTREQ · walkthrough 2026-07-21: <- 6M pin 5 (Q1) ~INT 16 $INTREQ +5V ~NMI 17 +5V +5V · drawn tied high here; revisit if 6/8 shows wait generation ~WAIT 24 +5V $BUSRQ · bus arbitration, to 6/8 ~BUSRQ 25 $BUSRQ /$RES ~RESET 26 /$RES A11 A11 1 A11 A12 A12 2 A12 A13 A13 3 A13 A14 A14 4 A14 A15 A15 5 A15 /MREQ ~MREQ 19 /MREQ /$IORQ ~IORQ 20 /$IORQ /RD ~RD 21 /RD /WR ~WR 22 /WR $BUSAK · to 6/8 ~BUSAK 23 $BUSAK /M1 ~M1 27 /M1 /RFSH ~RFSH 28 /RFSH A0 A0 30 A0 A1 A1 31 A1 A2 A2 32 A2 A3 A3 33 A3 A4 A4 34 A4 A5 A5 35 A5 A6 A6 36 A6 A7 A7 37 A7 A8 A8 38 A8 A9 A9 39 A9 A10 A10 40 A10 VCC:11=+5V GND:29=GND 9J — 74LS138: Memory decoder, 8kB blocks off A13-A15, qualified by /MREQ and disabled during refresh (G1 = /RFSH) — verified 2026-07-21 9J ✓ 74LS138 A13 A 1 A13 A14 B 2 A14 A15 C 3 A15 GND ~G2A 4 GND /MREQ ~G2B 5 /MREQ /RFSH · read from the drawing: 11M pin 28 feeds G1 - decoder off during refresh cycles (netlist previously guessed +5) G1 6 /RFSH /CSEF Y7 7 /CSEF /CSCD · C000-DFFF -> sheet 2/8 (I/O + char VRAM decode) Y6 9 /CSCD /CSAB Y5 10 /CSAB /CS89 Y4 11 /CS89 /CS67 Y3 12 /CS67 /CS45 Y2 13 /CS45 /CS23 Y1 14 /CS23 /CS01 Y0 15 /CS01 GND:8=GND VCC:16=+5V 9L — 74LS08: ROM chip-enable combiner (AND of active-low selects = OR of ranges). Unit 2 = 9M /CE (repaired on the dirty board: unit 4 in Fixes.txt numbering was broken) — verified 2026-07-21 9L ✓ 74LS08 /CS01 A1 1 /CS01 /CS23 B1 2 /CS23 $CS0123 A2 4 $CS0123 $CS4567 B2 5 $CS4567 /CS45 A3 9 /CS45 /CS67 B3 10 /CS67 /CS89 A4 12 /CS89 /CSAB B4 13 /CSAB $CS0123 Y1 3 $CS0123 /$CE9M Y2 6 /$CE9M $CS4567 Y3 8 $CS4567 /$CE8M Y4 11 /$CE8M GND:7=GND VCC:14=+5V 9M — 27256: Main program ROM 0000-7FFF (CM04, 250ns). On the clean board this socket carries the double-stacked D27128 pair that replaces the custom decryptor (see BOARDS.md) — verified 2026-07-21 9M ✓ 27256 A12 A12 2 A12 A7 A7 3 A7 A6 A6 4 A6 A5 A5 5 A5 A4 A4 6 A4 A3 A3 7 A3 A2 A2 8 A2 A1 A1 9 A1 A0 A0 10 A0 /$CE9M ~CE 20 /$CE9M A10 A10 21 A10 GND ~OE 22 GND A11 A11 23 A11 A9 A9 24 A9 A8 A8 25 A8 A13 A13 26 A13 D0 D0 11 D0 D1 D1 12 D1 D2 D2 13 D2 D3 D3 15 D3 D4 D4 16 D4 D5 D5 17 D5 D6 D6 18 D6 D7 D7 19 D7 VPP:1=+5V GND:14=GND A14:27=+5V VCC:28=+5V 8M — 27128: Main program ROM 8000-BFFF (CM03, 250ns). Shares the address + D bus with 9M — verified 2026-07-21 8M ✓ 27128 A12 A12 2 A12 A7 A7 3 A7 A6 A6 4 A6 A5 A5 5 A5 A4 A4 6 A4 A3 A3 7 A3 A2 A2 8 A2 A1 A1 9 A1 A0 A0 10 A0 /$CE8M ~CE 20 /$CE8M A10 A10 21 A10 GND ~OE 22 GND A11 A11 23 A11 A9 A9 24 A9 A8 A8 25 A8 A13 A13 26 A13 D0 D0 11 D0 D1 D1 12 D1 D2 D2 13 D2 D3 D3 15 D3 D4 D4 16 D4 D5 D5 17 D5 D6 D6 18 D6 D7 D7 19 D7 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 7M — HM6264P: 8kB work RAM E000-FFFF. Address bus carries (22Kx8)x2 pullups, data bus 22Kx8 — verified 2026-07-21 7M ✓ HM6264P A12 A12 2 A12 A7 A7 3 A7 A6 A6 4 A6 A5 A5 5 A5 A4 A4 6 A4 A3 A3 7 A3 A2 A2 8 A2 A1 A1 9 A1 A0 A0 10 A0 D0 D0 11 D0 D1 D1 12 D1 D2 D2 13 D2 D3 D3 15 D3 D4 D4 16 D4 D5 D5 17 D5 D6 D6 18 D6 D7 D7 19 D7 /$RAMCS ~CS1 20 /$RAMCS A10 A10 21 A10 /RD ~OE 22 /RD A11 A11 23 A11 A9 A9 24 A9 A8 A8 25 A8 +5V CS2 26 +5V /WR ~WE 27 /WR GND:14=GND VCC:28=+5V 6N — 74LS08: Work RAM chip-select: /CSEF (CPU access to E000-FFFF) OR /$BLCNTEN (sprite-DMA access from the B board) -> 7M /CS1 — verified 2026-07-21 6N ✓ 74LS08 BLCNTEN · walkthrough 2026-07-21: CN-1 B23 from the B board - opens the RAM for sprite DMA during blanking A2 4 BLCNTEN /CSEF B2 5 /CSEF drawn on a2-custom - click to jump there · /IN5 · <- a2-2-io 3A pin 10 (/IN5, C005 read strobe) - closes that sheet-2 open end B3 9 /IN5 ↗ drawn on a2-custom - click to jump there · /ACL1 · <- a2-1-cpu 11J pin 4. Continuity confirmed 2026-07-25 (and NOT /RES: 11J pin 8 read open) A3 10 /ACL1 ↗ drawn on a2-custom - click to jump there · $MREQ · <- 11J pin 2 ($MREQ) A4 12 $MREQ ↗ drawn on a2-custom - click to jump there · /RFSH · <- /RFSH B4 13 /RFSH ↗ /$RAMCS Y2 6 /$RAMCS drawn on a2-custom - click to jump there · $NRST10M · -> 10M pin 27 (NRST) Y3 8 $NRST10M ↗ drawn on a2-custom - click to jump there · $E10M · -> 10M pin 28 (E) Y4 11 $E10M ↗ GND:7=GND VCC:14=+5V 6L — TBP24S10: 256x4 interrupt timing PROM (7611), addressed by V counter V1-V128 from 5/8 - fires the scanline/vblank interrupt pattern — verified 2026-07-21 6L ✓ TBP24S10 V64 A6 1 V64 V32 A5 2 V32 V16 A4 3 V16 V8 A3 4 V8 V1 A0 5 V1 V2 A1 6 V2 V4 A2 7 V4 GND ~CE1 13 GND GND ~CE2 14 GND V128 A7 15 V128 $INTP3 · walkthrough 2026-07-21: -> 6M pin 12 (main-INT FF data) D3 9 $INTP3 $INTP2 · walkthrough 2026-07-21: -> 7L pin 11 (latched to Q4 = SOUND INT) D2 10 $INTP2 $INTP1 · walkthrough 2026-07-21: -> 11K pin 8 = vector bit D4-prime (RST 08/10 selector bit 4) D1 11 $INTP1 $INTP0 · walkthrough 2026-07-21: -> 11K pin 13 = vector bit D3-prime (RST 08/10 selector bit 3) D0 12 $INTP0 GND:8=GND VCC:16=+5V 7L — 74LS174: Hex FF in the interrupt chain (drawing says '174 - the netlist's earlier ''74' was wrong). Q4 (pin 10) = SOUND INT to 3/8. This is the IC that died in the dirty-board repair (no clock to 6M) — verified 2026-07-21 7L ✓ 74LS174 +5V ~CL 1 +5V $H1B · walkthrough 2026-07-21: <- 8K pin 11 (buffered scanline-rate clock), shared with 11K CLK CLK 9 $H1B $INTP2 D4 11 $INTP2 $INTQ2 · walkthrough 2026-07-21: <- 6M pin 9 (unit-2 Q) - one-clock delay stage in the INT edge chain D6 14 $INTQ2 SOUNDINT · to 3/8 (sound CPU periodic IRQ) Q4 10 SOUNDINT $INTQ6 · walkthrough 2026-07-21: -> 6M pin 3 (clocks the main-INT FF) Q6 15 $INTQ6 GND:8=GND VCC:16=+5V 6M — 74LS74: Dual D-FF, interrupt request generation (both units drawn separately). Exact unit wiring is the focus area - Fixes.txt: 7L feeds 6M's clock — verified 2026-07-21 6M ✓ 74LS74 +5V ~CL1 1 +5V GND · walkthrough 2026-07-21: D1 grounded - INT asserts (Q low... polarity per Q wiring) on the CLK edge, cleared via PR D1 2 GND $INTQ6 · walkthrough 2026-07-21: CLK1 <- 7L Q6 pin 15 (the dead-7L repair trace from Fixes.txt) CLK1 3 $INTQ6 /$INTACK · walkthrough 2026-07-21: <- 10J pin 3 (/$IORQ+M1 gate) - interrupt acknowledge presets the FF, releasing /INT ~PR1 4 /$INTACK +5V ~PR2 10 +5V $LHBLB · walkthrough 2026-07-21: <- 8K pin 13 (Y6, a second buffered clock channel - source signal into 8K pin 14 TBC) CLK2 11 $LHBLB $INTP3 D2 12 $INTP3 /$INTACK · walkthrough 2026-07-21: <- 10J pin 3 - acknowledge also clears the sampling FF (chain re-arms) ~CL2 13 /$INTACK $INTREQ · walkthrough 2026-07-21: -> Z80 pin 16 - THE interrupt request line Q1 5 $INTREQ $INTQ2 · walkthrough 2026-07-21: -> 7L pin 14 (D6) Q2 9 $INTQ2 GND:7=GND VCC:14=+5V 10J — 74LS32: Unit 1: /$IORQ OR /M1 = /$INTACK -> 11K OE + 6M preset/clear. Unit 2: /RDB OR /$BLCNTEN -> 8L DIR (reads pull data in; DMA forces data out) — verified 2026-07-21 10J ✓ 74LS32 /M1 B1 1 /M1 /$IORQ A1 2 /$IORQ /$BLCNTEN · walkthrough 2026-07-21: <- 11J pin 12 (/$BLCNTEN - 11J input confirmed as /$BLCNTEN) A2 4 /$BLCNTEN /RDB · walkthrough 2026-07-21: the interboard read strobe (10K pin 12 / CN-1 B25; B board drives it during DMA) B2 5 /RDB drawn on a2-3-sound - click to jump there · $SINTQ1 · A4 <- 8D pin 5 A4 12 $SINTQ1 ↗ drawn on a2-3-sound - click to jump there · /$SINTQ2 · B4 <- 8D pin 8 B4 13 /$SINTQ2 ↗ /$INTACK Y1 3 /$INTACK $DBDIR Y2 6 $DBDIR drawn on a2-3-sound - click to jump there · $SWAIT · -> 11F pin 24 /WAIT, clearly drawn Y4 11 $SWAIT ↗ GND:7=GND VCC:14=+5V 11K — 74LS374: Interrupt vector latch: straps spell 11x0x111 and the PROM drives bits 4+3 -> vectors 0xCF (RST 08) and 0xD7 (RST 10), the two per-frame interrupts MAME documents. Latched on INTCLK, jammed onto D-prime during /$INTACK — verified 2026-07-21 11K ✓ 74LS374 /$INTACK · walkthrough-confirmed 2026-07-21: <- 10J pin 3, shared with 6M PR1/CL2 ~OE 1 /$INTACK +5V D1 3 +5V +5V D2 4 +5V GND D3 7 GND $INTP1 · PROM-driven vector bit -> Q4 -> D4-prime D4 8 $INTP1 $H1B · walkthrough 2026-07-21: same clock as 7L - vector bits latch on the same edge as the INT pattern CLK 11 $H1B $INTP0 · PROM-driven vector bit -> Q5 -> D3-prime D5 13 $INTP0 +5V D6 14 +5V +5V D7 17 +5V +5V D8 18 +5V D7' Q1 2 D7' D6' Q2 5 D6' D5' Q3 6 D5' D4' Q4 9 D4' D3' Q5 12 D3' D2' Q6 15 D2' D1' Q7 16 D1' D0' Q8 19 D0' GND:10=GND VCC:20=+5V 10K — 74LS245: Address/strobe buffer to the interboard bus: A8-A12, /RD, /WR -> AB8-AB12, /RDB, /WRB (CN-1). Always enabled; DIR = /$BLCNTEN, so the B board reverses the buffers to address the work RAM during sprite DMA. see 8L note - identity among the three LS245s provisional — verified 2026-07-21 10K ✓ 74LS245 BLCNTEN · walkthrough 2026-07-21: NOT a tie - /$BLCNTEN reverses direction for sprite DMA DIR 1 BLCNTEN A10 A1 2 A10 A9 A2 3 A9 A8 A3 4 A8 A11 A4 5 A11 A12 A5 6 A12 /WR A6 7 /WR /RD A7 8 /RD GND ~G 19 GND /RDB B7 12 /RDB /WRB B6 13 /WRB AB12 B5 14 AB12 AB11 B4 15 AB11 AB8 B3 16 AB8 AB9 B2 17 AB9 AB10 B1 18 AB10 GND:10=GND VCC:20=+5V 9K — 74LS245: Address buffer to the interboard bus: A0-A7 -> AB0-AB7 (CN-1). Always enabled; DIR = /$BLCNTEN, so the B board reverses the buffers to address the work RAM during sprite DMA. see 8L note - identity among the three LS245s provisional — verified 2026-07-21 9K ✓ 74LS245 BLCNTEN · walkthrough 2026-07-21: NOT a tie - /$BLCNTEN reverses direction for sprite DMA DIR 1 BLCNTEN A1 A1 2 A1 A0 A2 3 A0 A7 A3 4 A7 A6 A4 5 A6 A5 A5 6 A5 A4 A6 7 A4 A3 A7 8 A3 A2 A8 9 A2 GND ~G 19 GND AB2 B8 11 AB2 AB3 B7 12 AB3 AB4 B6 13 AB4 AB5 B5 14 AB5 AB6 B4 15 AB6 AB7 B3 16 AB7 AB0 B2 17 AB0 AB1 B1 18 AB1 GND:10=GND VCC:20=+5V 8L — 74LS245: Data bus buffer: memory D bus <-> interboard DB bus (CN-1 A1-A8). Direction flips for reads from the video boards. one of the three LS245s in the CPU corner - which of 8L/9K/10K is which needs the walkthrough/board to confirm — verified 2026-07-21 8L ✓ 74LS245 $DBDIR DIR 1 $DBDIR D0 A1 2 D0 D1 A2 3 D1 D2 A3 4 D2 D3 A4 5 D3 D4 A5 6 D4 D5 A6 7 D5 D6 A7 8 D6 D7 A8 9 D7 DB7 B8 11 DB7 DB6 B7 12 DB6 DB5 B6 13 DB5 DB4 B5 14 DB4 DB3 B4 15 DB3 DB2 B3 16 DB2 DB1 B2 17 DB1 DB0 B1 18 DB0 /$DBEN ~G 19 /$DBEN GND:10=GND VCC:20=+5V 5K — 74LS08: Interboard data buffer enable: /CSCD (CPU in the C000-DFFF video/IO window) OR /$BLCNTEN (sprite DMA) -> 8L /G — verified 2026-07-21 5K ✓ 74LS08 BLCNTEN · walkthrough 2026-07-21 A2 4 BLCNTEN /CSCD · walkthrough 2026-07-21: tapped from 9J pin 9 (the C000-DFFF decode that also feeds sheet 2/8) B2 5 /CSCD drawn on a2-5-sync - click to jump there · $VSW · <- 5N pin 12 (decoded VSYNC window) B3 9 $VSW ↗ drawn on a2-5-sync - click to jump there · $HSYNC · <- 5K pin 11 A3 10 $HSYNC ↗ drawn on a2-5-sync - click to jump there · $HSW2 · <- 5L pin 11 B4 12 $HSW2 ↗ drawn on a2-5-sync - click to jump there · $HSW1 · <- 5L pin 12 A4 13 $HSW1 ↗ /$DBEN Y2 6 /$DBEN drawn on a2-5-sync - click to jump there · CMPSYNC · -> R58 220R -> CMP SYNC edge pin F | sheet letters it "CM P. SYNC" (composite sync); we drop the space and dot Y3 8 CMPSYNC ↗ drawn on a2-5-sync - click to jump there · $HSYNC · -> 5K pin 10 Y4 11 $HSYNC ↗ GND:7=GND VCC:14=+5V 8K — 74LS367: Hex buffer: PHIMAIN -> CPU clock, H1 -> 7L/11K clock, LHBL -> 6M sampling clock, /ROB -> 6/8, $BUSAK -> AKB (CN-1 B21, the DMA bus-grant to the B board). One channel spare — verified 2026-07-21 8K ✓ 74LS367 GND ~EN1 1 GND PHIMAIN · from 6/8 A1 2 PHIMAIN $BUSAK · walkthrough 2026-07-21: <- Z80 pin 23 - the bus grant, buffered out as AKB A3 6 $BUSAK /ROB · CN-1 B22 in A4 10 /ROB H1 · from 5/8 A5 12 H1 LHBL · from 5/8 A6 14 LHBL GND ~EN2 15 GND $PHICPU · -> Z80 pin 6 (560R pullup) Y1 3 $PHICPU /AKB · walkthrough 2026-07-21: CN-1 B21 - DMA bus-grant out to the B board | slash joined 2026-07-27 to match the B-board ends (CN-1 B21) Y3 7 /AKB $ROBB · to 6/8 Y4 9 $ROBB $H1B · walkthrough 2026-07-21: -> 7L pin 9 + 11K pin 11 Y5 11 $H1B $LHBLB · walkthrough 2026-07-21: -> 6M pin 11 (scanline-rate sampling clock) Y6 13 $LHBLB GND:8=GND VCC:16=+5V 11J — 74LS14: Hex Schmitt inverter: reset shaping (PST518 -> /$RES chain, /ACL1//ACL2 power-on clears) + /RDB inversion for the 8L direction gate — verified 2026-07-21 11J ✓ 74LS14 drawn on a2-custom - click to jump there · /MREQ · <- /$MREQ A1 1 /MREQ ↗ $RESNODE A2 3 $RESNODE drawn on a2-custom - click to jump there · /M1 · <- /M1 (C33 220pF to GND on this node) A3 5 /M1 ↗ $RESNODE A4 9 $RESNODE $PSTOUT A5 11 $PSTOUT BLCNTEN · walkthrough 2026-07-21: /$BLCNTEN in - inverter completes DIR = /RDB OR /$BLCNTEN A6 13 BLCNTEN drawn on a2-custom - click to jump there · $MREQ · -> 6N pin 12 Y1 2 $MREQ ↗ /ACL1 · driver. Drawn /ACL2 locally, leaves as /ACL1 on CN-1 B19 to 2/8 + 3/8. Single node - continuity confirmed 2026-07-25 Y2 4 /ACL1 drawn on a2-custom - click to jump there · $SYNC10M · -> 10M pin 47 (SYNC) Y3 6 $SYNC10M ↗ /$RES Y4 8 /$RES $RESNODE Y5 10 $RESNODE /$BLCNTEN Y6 12 /$BLCNTEN GND:7=GND VCC:14=+5V PST — PST518: Reset supervisor (11J area, with R56 220k / R57 47R / CC17 4.7uF shaping) — verified 2026-07-21 PST ✓ PST518 $PSTOUT OUT 3 $PSTOUT VCC:1=+5V GND:2=GND
· Original scan — manual p23 · zoom
original schematic scan
11M
9J
9L
9M
8M
7M
6N
6L
7L
6M
10J
11K
10K
9K
8L
5K
8K
11J
PST