85605-A-2 Sheet 3/8: SOUND BY PSG

manual p25 · 14 ICs · 14 verified ✓ · layout mirrors the original drawing
Click a net label to trace it, with endpoints colour-coded input · output · in/out. Click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is one I coined for a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
11F Z80A: Sound CPU (NEC D780C on the board - replaced with new socket in the repair). PhiB 3MHz clock, periodic /INT ~4x frame. NC: 18 (HALT), 23 (BUSAK), 27 (M1) per the drawing (verified 2026-07-25) 11F ✓ Z80A $PHIBZ · phi clock <- 8E pin 7 (Robert-confirmed 2026-07-25) PHI 6 $PHIBZ $SD4 D4 7 $SD4 $SD3 D3 8 $SD3 $SD5 D5 9 $SD5 $SD6 D6 10 $SD6 $SD2 D2 12 $SD2 $SD7 D7 13 $SD7 $SD0 D0 14 $SD0 $SD1 D1 15 $SD1 $SINTREQ · ~INT <- 11E pin 5 ~INT 16 $SINTREQ +5V ~NMI 17 +5V $SWAIT · ~WAIT <- 10J pin 11 ~WAIT 24 $SWAIT +5V ~BUSRQ 25 +5V /$SRES · ~RESET = /$SRES (CPUBRES from 7A/1-8); shared with 9C pin 24 (YM /IC) ~RESET 26 /$SRES $SA11 A11 1 $SA11 $SA12 A12 2 $SA12 $SA13 A13 3 $SA13 $SA14 A14 4 $SA14 $SA15 A15 5 $SA15 /$SMREQ · ~MREQ -> 10E pin 4 ~MREQ 19 /$SMREQ /$SIORQ · ~IORQ -> 11E pin 4 ~IORQ 20 /$SIORQ /$SRD · ~RD /$SRD -> 8F.20 + 9F.22 ~RD 21 /$SRD /$SWR · ~WR /$SWR -> 8E pin 12 (buffered to /$SWRB) ~WR 22 /$SWR /$SRFSH · ~RFSH -> 10E pin 6 ~RFSH 28 /$SRFSH $SA0 A0 30 $SA0 $SA1 A1 31 $SA1 $SA2 A2 32 $SA2 $SA3 A3 33 $SA3 $SA4 A4 34 $SA4 $SA5 A5 35 $SA5 $SA6 A6 36 $SA6 $SA7 A7 37 $SA7 $SA8 A8 38 $SA8 $SA9 A9 39 $SA9 $SA10 A10 40 $SA10 VCC:11=+5V GND:29=GND 10E 74LS138: Sound memory decoder, 8kB blocks; G1 = /RFSH (refresh-disable, same trick as the main CPU decoder) (verified 2026-07-25) 10E ✓ 74LS138 $SA13 A 1 $SA13 $SA14 B 2 $SA14 $SA15 C 3 $SA15 /$SMREQ · ~G2A <- 11F pin 19 /MREQ ~G2A 4 /$SMREQ GND ~G2B 5 GND /$SRFSH · G1 <- 11F pin 28 /RFSH (decode off during refresh) G1 6 /$SRFSH /$SYMEN · Y4 8000-9FFF /$SYMEN -> 7C pin 1 + 8D pin 2 Y4 11 /$SYMEN /$SLATCH · Y3 6000-7FFF /$SLATCH -> 8J pin 1 (~OC) Y3 12 /$SLATCH /$SRAMCS · Y2 4000-5FFF /$SRAMCS -> 8F pin 18 Y2 13 /$SRAMCS /$SC23 · Y1 2000-3FFF /$SC23 -> 6F pin 1 Y1 14 /$SC23 /$SC01 · Y0 0000-1FFF /$SC01 -> 6F pin 2 Y0 15 /$SC01 GND:8=GND VCC:16=+5V 6F 74LS08: ROM CE combiner: 0000-1FFF OR 2000-3FFF -> 9F /CE (single gate used on this sheet) (verified 2026-07-25) 6F ✓ 74LS08 /$SC23 · <- 10E pin 14 A1 1 /$SC23 /$SC01 · <- 10E pin 15 B1 2 /$SC01 drawn on a2-6-charvram - click to jump there · /$CHEN · <- 4H pin 8 B3 9 /$CHEN ↗ drawn on a2-6-charvram - click to jump there · $D0CS · <- 3E pin 6 | renamed 2026-07-27: same net as io 3B pin 6 /$D0CS (D000-D7FF) - was a letter-O vs zero split A3 10 $D0CS ↗ drawn on a2-6-charvram - click to jump there · /$H4C · <- 4K pin 2 B4 12 /$H4C ↗ drawn on a2-6-charvram - click to jump there · H2 · H2 display | joined 2026-07-27: arrives from 5/8 3K pin 13, not a locally-made variant A4 13 H2 ↗ /$SROMCE · /$SROMCE low for 0000-3FFF -> 9F ~CE Y1 3 /$SROMCE drawn on a2-6-charvram - click to jump there · $ARBCL · -> 4H pin 1 ~CL (ends CPU grant) Y3 8 $ARBCL ↗ drawn on a2-6-charvram - click to jump there · $CHLD · -> 6E CLK (display fetch strobe) Y4 11 $CHLD ↗ GND:7=GND VCC:14=+5V 9F 27128: Sound program ROM (CM02 - the one replaced on the clean board, 'D5/ROM1' in Fixes.txt is the char ROM; this is cm02.9f). Board box provisional (verified 2026-07-25) 9F ✓ 27128 $SA12 A12 2 $SA12 $SA7 A7 3 $SA7 $SA6 A6 4 $SA6 $SA5 A5 5 $SA5 $SA4 A4 6 $SA4 $SA3 A3 7 $SA3 $SA2 A2 8 $SA2 $SA1 A1 9 $SA1 $SA0 A0 10 $SA0 /$SROMCE · ~CE <- 6F pin 3 /$SROMCE ~CE 20 /$SROMCE $SA10 A10 21 $SA10 /$SRD · ~OE <- 11F pin 21 /RD (sound read strobe /$SRD) ~OE 22 /$SRD $SA11 A11 23 $SA11 $SA9 A9 24 $SA9 $SA8 A8 25 $SA8 $SA13 A13 26 $SA13 $SD0 D0 11 $SD0 $SD1 D1 12 $SD1 $SD2 D2 13 $SD2 $SD3 D3 15 $SD3 $SD4 D4 16 $SD4 $SD5 D5 17 $SD5 $SD6 D6 18 $SD6 $SD7 D7 19 $SD7 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 8F M58725: 2kB sound work RAM (4000-47FF). RA8 22Kx8 pullups on the sound data bus (verified 2026-07-25) 8F ✓ M58725 $SA7 A7 1 $SA7 $SA6 A6 2 $SA6 $SA5 A5 3 $SA5 $SA4 A4 4 $SA4 $SA3 A3 5 $SA3 $SA2 A2 6 $SA2 $SA1 A1 7 $SA1 $SA0 A0 8 $SA0 $SD0 D0 9 $SD0 $SD1 D1 10 $SD1 $SD2 D2 11 $SD2 $SD3 D3 13 $SD3 $SD4 D4 14 $SD4 $SD5 D5 15 $SD5 $SD6 D6 16 $SD6 $SD7 D7 17 $SD7 /$SRAMCS · ~CE <- /$SRAMCS (10E pin 13) ~CE 18 /$SRAMCS $SA10 A10 19 $SA10 /$SRD · ~OE <- /$SRD (11F pin 21 /RD), same as 9F pin 22 ~OE 20 /$SRD /$SWRB · ~WE <- /$SWR = 8E pin 11 (buffers 11F pin 22 /WR) ~WE 21 /$SWRB $SA9 A9 22 $SA9 $SA8 A8 23 $SA8 GND:12=GND VCC:24=+5V 8J 74LS374: Sound command latch: main CPU writes C800 (OUT0 clock), sound CPU reads at 6000-7FFF. The only crossing between the two bus systems (verified 2026-07-25) 8J ✓ 74LS374 /$SLATCH · ~OC <- 10E pin 12 (sound reads mailbox at 6000-7FFF) ~OC 1 /$SLATCH DB3 D1 3 DB3 DB2 D2 4 DB2 DB1 D3 7 DB1 DB0 D4 8 DB0 OUT0 · CLK <- /OUT0 (main C800 write, from 2/8) | no overbar on the sheet (Robert, 2026-07-27) CLK 11 OUT0 DB7 D5 13 DB7 DB6 D6 14 DB6 DB5 D7 17 DB5 DB4 D8 18 DB4 $SD3 Q1 2 $SD3 $SD2 Q2 5 $SD2 $SD1 Q3 6 $SD1 $SD0 Q4 9 $SD0 $SD7 Q5 12 $SD7 $SD6 Q6 15 $SD6 $SD5 Q7 16 $SD5 $SD4 Q8 19 $SD4 GND:10=GND VCC:20=+5V 8D 74LS74: Sound INT-request FF pair, both PhiB-clocked: unit1 D=/$SYMEN -> Q1=$SINTQ1 (-> 10J.12 + unit2 D); unit2 -> /Q2=/$SINTQ2 (-> 10J.13 WAIT gate). Q2 (pin 9) is unused - no track on the board; the WAIT gate only needs /Q2 (verified 2026-07-25) 8D ✓ 74LS74 +5V ~CL1 1 +5V /$SYMEN · D1 <- 10E pin 11 D1 2 /$SYMEN $PHIBB · CLK1 <- 8E pin 5 (buffered PhiB), NOT SOUNDINT CLK1 3 $PHIBB +5V ~PR1 4 +5V +5V ~PR2 10 +5V $PHIBB · CLK2 <- 8E pin 5 (both units PhiB-clocked) CLK2 11 $PHIBB $SINTQ1 · D2 <- Q1 (pin5) D2 12 $SINTQ1 +5V ~CL2 13 +5V $SINTQ1 · Q1 -> D2 (pin12) + 10J pin 12 Q1 5 $SINTQ1 /$SINTQ2 · ~Q2 -> 10J pin 13 ~Q2 8 /$SINTQ2 GND:7=GND VCC:14=+5V 11E 74LS74: Dual 74: unit1 = INT delivery latch (D=GND, CLK=$SINTB, ~PR=/$SIORQ ack, Q1=$SINTREQ->11F /INT); unit2 = divide-by-2 making the 1.5MHz YM clock phi-M (D=/Q toggle, CLK=3MHz PhiB, Q2->9C pin 38) (verified 2026-07-25) 11E ✓ 74LS74 +5V ~CL1 1 +5V GND · D1 grounded D1 2 GND $SINTB · CLK1 <- 8E pin 3 (SOUNDINT pulse) CLK1 3 $SINTB /$SIORQ · ~PR1 <- 11F pin 20 /IORQ (INT ack clears /INT) ~PR1 4 /$SIORQ +5V ~PR2 10 +5V $PHIBB · CLK2 <- 8E pin 5 (3MHz PhiB) CLK2 11 $PHIBB /$PHIM · D2 <- ~Q2 (pin8) D2 12 /$PHIM +5V ~CL2 13 +5V $SINTREQ · Q1 $SINTREQ -> 11F pin 16 /INT Q1 5 $SINTREQ /$PHIM · divide-by-2 feedback -> 11E pin 12 (D2) ~Q2 8 /$PHIM PHIM · Q2 = 1.5MHz YM clock (phi-M) -> 9C pin 38 (and likely 11C) Q2 9 PHIM GND:7=GND VCC:14=+5V 10J 74LS32: Gate 4 = $SINTQ1 OR /$SINTQ2 -> $SWAIT -> 11F pin 24 (holds sound CPU in WAIT per INT-request state). Gates 1-3 not drawn on this sheet (shared package). Gate 3 (pins 9,10->8) is unused: drawn on neither 1/8 nor 3/8 and no tracks on the board. Gates 1-2 are on sheet 1/8, gate 4 here. (verified 2026-07-25) 10J ✓ 74LS32 drawn on a2-1-cpu - click to jump there · /M1 B1 1 /M1 ↗ drawn on a2-1-cpu - click to jump there · /$IORQ A1 2 /$IORQ ↗ drawn on a2-1-cpu - click to jump there · /$BLCNTEN · walkthrough 2026-07-21: <- 11J pin 12 (/$BLCNTEN - 11J input confirmed as /$BLCNTEN) A2 4 /$BLCNTEN ↗ drawn on a2-1-cpu - click to jump there · /RDB · walkthrough 2026-07-21: the interboard read strobe (10K pin 12 / CN-1 B25; B board drives it during DMA) B2 5 /RDB ↗ $SINTQ1 · A4 <- 8D pin 5 A4 12 $SINTQ1 /$SINTQ2 · B4 <- 8D pin 8 B4 13 /$SINTQ2 drawn on a2-1-cpu - click to jump there · /$INTACK Y1 3 /$INTACK ↗ drawn on a2-1-cpu - click to jump there · $DBDIR Y2 6 $DBDIR ↗ $SWAIT · -> 11F pin 24 /WAIT, clearly drawn Y4 11 $SWAIT GND:7=GND VCC:14=+5V 8E 74LS367: 367 buffer: SOUNDINT->$SINTB (11E.3 clk), PhiB->$PHIBB (8D.3+11E.11 clks + buffer3) ->$PHIBZ (11F.6 Z80 clk), /WR->/$SWRB (8F.21), /ACL1->/$SRES (11F.26+9C.24). Buffer 4 spare, both enables GND (verified 2026-07-25) 8E ✓ 74LS367 GND ~EN1 1 GND SOUNDINT · A1 SOUND INT from 1/8 A1 2 SOUNDINT PHIB · A2 PhiB clock in (3K.9 via cable) A2 4 PHIB $PHIBB · buffer 3 in <- 8E pin 5 A3 6 $PHIBB /$SWR · A5 <- 11F pin 22 A5 12 /$SWR /ACL1 · A6 reset in <- 11J pin 4 via CN-1 B19 (same node as /ACL2) A6 14 /ACL1 GND ~EN2 15 GND $SINTB · Y1 -> 11E pin 3 (CLK1) Y1 3 $SINTB $PHIBB · Y2 buffered PhiB -> 11E.11, 8D.3, 8E.6 Y2 5 $PHIBB $PHIBZ · buffer 3 out -> 11F pin 6 (Z80 clock) Y3 7 $PHIBZ /$SWRB · Y5 -> 8F pin 21 Y5 11 /$SWRB /$SRES · Y6 -> 11F pin 26 + 9C pin 24 (YM /IC) Y6 13 /$SRES GND:8=GND VCC:16=+5V 7C 74LS139: YM2203 register select: A=$SA0, B=$SA1 within 8000-9FFF -> four strobes for the two chips (8000-8003, matching MAME) (verified 2026-07-25) 7C ✓ 74LS139 /$SYMEN · ~EN <- 10E pin 11 /$SYMEN (also to 8D pin 2) ~EN 1 /$SYMEN $SA0 A 2 $SA0 $SA1 B 3 $SA1 /$YMS0 · /$YMS0 (8000) -> 9E pins 9,10,12 Y0 4 /$YMS0 /$YMS1 · /$YMS1 (8001) -> 9E pin 13 Y1 5 /$YMS1 /$YMS2 · /$YMS2 (8002) -> 9E pins 2,4,5 Y2 6 /$YMS2 /$YMS3 · /$YMS3 (8003) -> 9E pin 1 Y3 7 /$YMS3 GND:8=GND VCC:16=+5V 9E 74LS08: YM2203 select logic off 7C. Drawn with the De Morgan symbol (bubbles on inputs and output), which is an AND: the output goes low when EITHER active-low select goes low. g1 combines /$YMS2 and /$YMS3 -> 9C pin 34 chip-2 /CS; g4 combines /$YMS0 and /$YMS1 -> 11C pin 34 chip-1 /CS. g2 and g3 are spare gates used as buffers, both inputs tied: g2 buffers /$YMS2 -> 9C pin 37 A0, g3 buffers /$YMS0 -> 11C pin 37 A0, so A0 is low at the register address (8000/8002) and high at the data address (8001/8003). Part corrected 74LS32 -> 74LS08 on 2026-07-27: both physical boards are silkscreened and populated LS08, and only AND gives the right chip-select behaviour. (verified 2026-07-25) 9E ✓ 74LS08 /$YMS3 · <- 7C B1 1 /$YMS3 /$YMS2 · <- 7C A1 2 /$YMS2 /$YMS2 · both inputs of gate 2 tied to the same line as gate 1 pin 2 - the OR is used as a buffer (Robert, 2026-07-27) A2 4 /$YMS2 /$YMS2 · both inputs of gate 2 tied to the same line as gate 1 pin 2 - the OR is used as a buffer (Robert, 2026-07-27) B2 5 /$YMS2 /$YMS0 · both inputs of gate 3 tied to the same line as gate 4 pin 12 - the OR is used as a buffer (Robert, 2026-07-27) A3 9 /$YMS0 /$YMS0 · both inputs of gate 3 tied to the same line as gate 4 pin 12 - the OR is used as a buffer (Robert, 2026-07-27) B3 10 /$YMS0 /$YMS0 · <- 7C A4 12 /$YMS0 /$YMS1 · <- 7C B4 13 /$YMS1 /$YMCS2 · gate1 /$YMS2|/$YMS3 -> 9C pin 34 (chip2 /CS) Y1 3 /$YMCS2 /$YMS2B · gate2 buffered /$YMS2 -> 9C pin 37 (A0) Y2 6 /$YMS2B /$YMS0B · gate3 buffered /$YMS0 -> 11C pin 37 (A0) Y3 8 /$YMS0B /$YMCS1 · gate4 /$YMS0|/$YMS1 -> 11C pin 34 (chip1 /CS) Y4 11 /$YMCS1 GND:7=GND VCC:14=+5V 9C YM2203: YM2203 chip2 8002/8003 (9C): data $SD0-7, /CS from 9E, A0 /$YMS2B, /RD tied +5 (write-only), /WR tied GND, clock 1.5MHz phi-M (11E.9), reset /$SRES. SSG A/B/C + FM OUT -> 4/8 amp (SH/phi-S = DAC timing). I/O ports and /IRQ not wired (unmodelled) (verified 2026-07-25) 9C ✓ YM2203 $SD1 D1 2 $SD1 $SD2 D2 3 $SD2 $SD3 D3 4 $SD3 $SD4 D4 5 $SD4 $SD5 D5 6 $SD5 $SD6 D6 7 $SD6 $SD7 D7 8 $SD7 /$SRES · ~IC reset = /$SRES (11F pin 26) ~IC 24 /$SRES /$YMCS2 · ~CS ~CS 34 /$YMCS2 GND · ~WR tied low - write gated by /CS ~WR 35 GND +5V · ~RD tied high - YM never read, write-only via /CS ~RD 36 +5V /$YMS2B · A0 <- 9E pin 6 A0 37 /$YMS2B PHIM · 1.5MHz clock <- 11E pin 9 PHIM 38 PHIM $SD0 D0 40 $SD0 $SSG2C · to 4/8 -> 4/8 main amp C 18 $SSG2C $SSG2B · to 4/8 -> 4/8 main amp B 19 $SSG2B $SSG2A · to 4/8 mixer -> 4/8 main amp A 20 $SSG2A 2SH · to 4/8 SH 22 2SH 2OUT · FM serial to 4/8 (YM3014) -> 4/8 main amp OUT 23 2OUT 2PHIS · to 4/8 (YM3014 clock) PHIS 39 2PHIS GND:1=GND AGND:17=GND VCC:21=+5V 11C YM2203: YM2203 chip1 8000/8001 (11C): data $SD0-7, /CS from 9E, A0 /$YMS0B, /RD tied +5 (write-only), /WR tied GND, clock 1.5MHz phi-M (11E.9), reset /$SRES. SSG A/B/C + FM OUT -> 4/8 amp (SH/phi-S = DAC timing). I/O ports and /IRQ not wired (unmodelled) (verified 2026-07-25) 11C ✓ YM2203 $SD1 D1 2 $SD1 $SD2 D2 3 $SD2 $SD3 D3 4 $SD3 $SD4 D4 5 $SD4 $SD5 D5 6 $SD5 $SD6 D6 7 $SD6 $SD7 D7 8 $SD7 /$SRES · ~IC reset = /$SRES (11F pin 26) ~IC 24 /$SRES /$YMCS1 · ~CS ~CS 34 /$YMCS1 GND · ~WR tied low - write gated by /CS ~WR 35 GND +5V · ~RD tied high - YM never read, write-only via /CS ~RD 36 +5V /$YMS0B · A0 <- 9E pin 8 A0 37 /$YMS0B PHIM · 1.5MHz clock <- 11E pin 9 PHIM 38 PHIM $SD0 D0 40 $SD0 $SSG1C · to 4/8 -> 4/8 main amp C 18 $SSG1C $SSG1B · to 4/8 -> 4/8 main amp B 19 $SSG1B $SSG1A · to 4/8 mixer -> 4/8 main amp A 20 $SSG1A 1SH · to 4/8 SH 22 1SH 1OUT · to 4/8 -> 4/8 main amp OUT 23 1OUT 1PHIS · to 4/8 PHIS 39 1PHIS GND:1=GND AGND:17=GND VCC:21=+5V
· Original scan, manual p25 · zoom
original schematic scan
11F
10E
6F
9F
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8J
8D
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10J
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11C