85605-A-2 Sheet 5/8 — SYNCHRONOUS

manual p27 · 19 ICs · 19 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Interboard connectors (the band cables between the boards) — circled letter+number labels on the drawing are connector row + pin
2N — 74LS04: Hex inverter: 12MHz crystal oscillator (XL1 + R60-R63/R69, C31/C32; osc loop 9->8, 11->10, 5->6 with pin 10 driving the crystal, pin 6 = clean $CLK12M -> 2M) plus the two reload strobes: 1&3 paralleled on $HCARRY -> /HINIT (pin 4 local reload, pin 2 second copy), 13 on $VCARRY -> /$VINIT (pin 12) — verified 2026-07-25 2N ✓ 74LS04 $HCARRY · <- 1K.15 CA (net also on 1M.12 and 2N.3) A1 1 $HCARRY $HCARRY · paralleled with pin 1 A2 3 $HCARRY $OSC12M · crystal hot side (same node as 2N.10 out + R69) A3 5 $OSC12M $OSCA · crystal cold side via C31; also fed from pin 8 through R62 (220R) A4 9 $OSCA $OSCB · RC node: R69 from crystal side + C32/R61 to GND A5 11 $OSCB $VCARRY · <- 1L.15 CA A6 13 $VCARRY /HINITB · second /HINIT copy -> CN-2 C18 -> B board 2/6 (8B pin 5 + 10B pin 10). Destination confirmed 2026-07-26 from the B-board walkthrough Y1 2 /HINITB /HINIT · -> 2K.9 + 1K.9 (~LD): reloads H counter to 128 Y2 4 /HINIT $CLK12M · clean 12MHz -> 2M pin 3 Y3 6 $CLK12M $OSCFB · oscillator feedback: -> C32, and via R62 (220R) to the C31 / pin 9 node ($OSCA). Confirmed 2026-07-27 Y4 8 $OSCFB $OSC12M · drives the crystal hot side directly Y5 10 $OSC12M /$VINIT · -> 1L.9 + 2L.9 (~LD): reloads V counter to 125 Y6 12 /$VINIT GND:7=GND VCC:14=+5V 2M — 74LS74: 12MHz crystal osc feeds this dual-74: unit 1 divides 12->6MHz (Q1 pin5=L6M, /Q1 pin6=X6M, the two 6M phases); unit 2 divides 6->3MHz (Q2 pin9=H1). H1 gates the H counter; X6M clocks it. — verified 2026-07-21 2M ✓ 74LS74 +5V ~CL1 1 +5V X6M D1 2 X6M $CLK12M CLK1 3 $CLK12M +5V ~PR1 4 +5V +5V ~PR2 10 +5V X6M · unit-2 clock = X6M (confirmed) CLK2 11 X6M /H1 D2 12 /H1 +5V ~CL2 13 +5V L6M Q1 5 L6M X6M ~Q1 6 X6M /H1 ~Q2 8 /H1 H1 Q2 9 H1 GND:7=GND VCC:14=+5V 3K — 74LS367: Timing buffer: X6M->6M (CN-2 C3, 7/8), /H1->PhiB (3MHz sound/arbiter clock, 3/8+6/8), /$XH4->H4 (C6), XH2->H2 (D5). Buffers 6/7 and 11/12 spare; both enables grounded — verified 2026-07-25 3K ✓ 74LS367 GND · enable grounded - always on ~G1 1 GND X6M · <- 2M.6 (/Q1) A1 2 X6M XH4 · <- 2K.13 QB A2 4 XH4 /H1 · <- 2M.12/8 (~Q2 node) A4 10 /H1 XH2 · <- 2K.14 QA A6 14 XH2 GND · enable grounded - always on ~G2 15 GND 6M · -> CN-2 C3 + sheet 7/8 Y1 3 6M H4 · -> CN-2 C6 + 6/8 Y2 5 H4 PHIB · phi-B 3MHz -> 3/8 sound (11E) + 6/8 charvram (5H) Y4 9 PHIB H2 · -> CN-2 D5 + 6/8 Y6 13 H2 GND:8=GND VCC:16=+5V 2K — 74LS161: H counter low: XH2/XH4/H8/H16, clocked at X6M, preloaded via /HINIT for the 384-clock line — verified 2026-07-21 2K ✓ 74LS161 +5V ~CL 1 +5V X6M CLK 2 X6M GND A 3 GND GND B 4 GND GND C 5 GND GND D 6 GND H1 · count-enable gated by H1 -> counter advances at 3MHz pixel rate P 7 H1 /HINIT · from 2N pin 4 ~LO 9 /HINIT H1 · count-enable gated by H1 -> counter advances at 3MHz pixel rate T 10 H1 H16 QD 11 H16 H8 QC 12 H8 XH4 QB 13 XH4 XH2 QA 14 XH2 $HCA1 · -> 1K enables CA 15 $HCA1 GND:8=GND VCC:16=+5V 1K — 74LS161: H counter high: H32-H256; carry -> VCLK chain — verified 2026-07-21 1K ✓ 74LS161 +5V ~CL 1 +5V X6M CLK 2 X6M GND A 3 GND GND B 4 GND +5V C 5 +5V GND D 6 GND $HCA1 P 7 $HCA1 /HINIT ~LO 9 /HINIT $HCA1 T 10 $HCA1 H256 QD 11 H256 H128 QC 12 H128 H64 QB 13 H64 H32 QA 14 H32 $HCARRY · -> 2N inverter -> 1M VCLK FFs CA 15 $HCARRY GND:8=GND VCC:16=+5V 1M — 74LS74: End-of-line FFs: unit 1 shapes VCLK from the H carry, unit 2 is the /$V1 toggle (/$V1 -> CN-2 C10 + the V counters) — verified 2026-07-21 1M ✓ 74LS74 +5V ~CL2 1 +5V /$V1 D2 2 /$V1 VCLK CLK2 3 VCLK +5V ~PR2 4 +5V +5V ~PR1 10 +5V X6M · reclock for VCLK shaper CLK1 11 X6M $HCARRY · D1 <- 1K.15 CA (same net as 2N.1/3). Name aligned 2026-07-25 per Robert read (was /$HCARRY) D1 12 $HCARRY +5V ~CL1 13 +5V V1 Q2 5 V1 /$V1 ~Q2 6 /$V1 VCLK Q1 9 VCLK GND:7=GND VCC:14=+5V 2L — 74LS161: V counter low: V2-V16 — verified 2026-07-21 2L ✓ 74LS161 +5V ~CL 1 +5V VCLK CLK 2 VCLK +5V A 3 +5V GND B 4 GND +5V C 5 +5V +5V D 6 +5V V1 · count-enable gated by /$V1 (1M pin 5) -> V counter advances every 2 lines P 7 V1 /$VINIT · from 2N pin 12 ~LO 9 /$VINIT V1 · count-enable gated by /$V1 (1M pin 5) T 10 V1 V16 QD 11 V16 V8 QC 12 V8 V4 QB 13 V4 V2 QA 14 V2 $VCA1 CA 15 $VCA1 GND:8=GND VCC:16=+5V 1L — 74LS161: V counter high: V32-V256 (the wonky-sync/no-picture repair IC on the dirty board) — verified 2026-07-21 1L ✓ 74LS161 +5V ~CL 1 +5V VCLK CLK 2 VCLK +5V A 3 +5V +5V B 4 +5V +5V C 5 +5V GND D 6 GND $VCA1 P 7 $VCA1 /$VINIT · from 2N pin 12 ~LO 9 /$VINIT $VCA1 T 10 $VCA1 V256 QD 11 V256 V128 QC 12 V128 V64 QB 13 V64 V32 QA 14 V32 $VCARRY · CA -> 2N.13 (V reload chain). Corrected 2026-07-25 during the 2N walkthrough; earlier read had NC CA 15 $VCARRY GND:8=GND VCC:16=+5V 3N — 74LS30: 8-input NAND: V16*V32*V64*/$V128*V256 (three inputs strapped +5) -> low at V count 248, sets the VSYNC latch via 5M ~PR2. Pins 9/10/13 are factory NC — verified 2026-07-25 3N ✓ 74LS30 V16 A 1 V16 V128 B 2 V128 V256 C 3 V256 V32 D 4 V32 V64 E 5 V64 +5V F 6 +5V +5V G 11 +5V +5V H 12 +5V /$VSSET · -> 5M pin 4 (~PR2): sets the VSYNC latch at count 248 Y 8 /$VSSET GND:7=GND VCC:14=+5V 5L — 74LS138: $HSYNC window decode off H16/H32/H64, gated by H256 low - two outputs combine in 5K — verified 2026-07-25 5L ✓ 74LS138 H16 A 1 H16 H32 B 2 H32 H64 C 3 H64 H256 ~G2A 4 H256 GND ~G2B 5 GND +5V G1 6 +5V $HSW2 · Y4 -> 5K pin 12 Y4 11 $HSW2 $HSW1 · Y3 -> 5K pin 13 Y3 12 $HSW1 GND:8=GND VCC:16=+5V 5N — 74LS138: VSYNC window decode off V8/V128/V256 -> 5M FF — verified 2026-07-21 5N ✓ 74LS138 V8 A 1 V8 V128 B 2 V128 V256 C 3 V256 $VSYNCQ · ~G2A <- 5M pin 6 (VSYNC latch feedback) ~G2A 4 $VSYNCQ GND ~G2B 5 GND +5V G1 6 +5V $VSW · Y3 (VSYNC window) -> 5K pin 9 (composite sync gate). Destination corrected 2026-07-25 per Robert (old note said 5M D1) Y3 12 $VSW GND:8=GND VCC:16=+5V 5M — 74LS74: Sync/blanking FFs: unit 1 latches the VSYNC window -> LVBL (to 8/8); unit 2 in the VBL chain (D from the 4L decode) — verified 2026-07-21 5M ✓ 74LS74 $VBLW · ~CL2 RESET <- 4L pin 6 ($VBLW) ~CL2 1 $VBLW GND · D2 grounded - unit 2 is an SR latch D2 2 GND GND · CLK2 grounded - unit 2 is an SR latch CLK2 3 GND /$VSSET · ~PR2 SET <- 3N pin 8 ~PR2 4 /$VSSET +5V ~PR1 10 +5V OH · joined 2026-07-27: the sheet labels 4M pin 6 OH in both places (out to 6/8 and to CN-2 D3); PHM2NQ was our invented name, so the driver never joined its consumers CLK1 11 OH $VSYNCQ · D1 <- $VSYNCQ (5M pin 6 / 5N pin 4) D1 12 $VSYNCQ +5V ~CL1 13 +5V $VSYNCQ · SR-latch out: set 3N.8, reset 4L.6; -> 5M pin 12 (D1) + 5N pin 4 (~G2A) ~Q2 6 $VSYNCQ LVBL · -> 8/8 Q1 9 LVBL GND:7=GND VCC:14=+5V 5K — 74LS08: Sync combiner: $HSW1*$HSW2 -> $HSYNC (pin 11), $HSYNC*$VSW -> CMPSYNC (pin 8) -> R58 220R -> CMP SYNC edge F. Gates 1+2 not drawn on this sheet - revisit after board A. Gate 1 (pins 1,2->3) is unused: drawn on neither 1/8 nor 5/8 and no tracks on the board. — verified 2026-07-25 5K ✓ 74LS08 drawn on a2-1-cpu - click to jump there · BLCNTEN · walkthrough 2026-07-21 A2 4 BLCNTEN ↗ drawn on a2-1-cpu - click to jump there · /CSCD · walkthrough 2026-07-21: tapped from 9J pin 9 (the C000-DFFF decode that also feeds sheet 2/8) B2 5 /CSCD ↗ $VSW · <- 5N pin 12 (decoded VSYNC window) B3 9 $VSW $HSYNC · <- 5K pin 11 A3 10 $HSYNC $HSW2 · <- 5L pin 11 B4 12 $HSW2 $HSW1 · <- 5L pin 12 A4 13 $HSW1 drawn on a2-1-cpu - click to jump there · /$DBEN Y2 6 /$DBEN ↗ CMPSYNC · -> R58 220R -> CMP SYNC edge pin F | sheet letters it "CM P. SYNC" (composite sync); we drop the space and dot Y3 8 CMPSYNC $HSYNC · -> 5K pin 10 Y4 11 $HSYNC GND:7=GND VCC:14=+5V 3L — 74LS112: Horizontal blanking JK: set/reset from the H-decode gates; /Q = LHBL (to 1/8, 8/8, CN-2 D9) — verified 2026-07-21 3L ✓ 74LS112 +5V ~PR 10 +5V $PH4Y · J <- 3M pin 11 J 11 $PH4Y $PH3Y · K <- 3M pin 8 K 12 $PH3Y L6M · from 2M pin 5 (was mis-read as X6M) CLK 13 L6M +5V ~CL 14 +5V LHBL · no overbar on the sheet (Robert, 2026-07-27) -> 1/8 (8K), 8/8, CN-2 D9 ~Q 7 LHBL GND:8=GND VCC:16=+5V 4L — 74LS10: Triple NAND: unit 1 = H1*XH2*/$XH4 sub-tile decode; unit 2 = VBL window decode (V16/V128/V256 group) — verified 2026-07-21 4L ✓ 74LS10 /$V128 · <- 4K pin 6 A2 3 /$V128 V256 B2 4 V256 V16 C2 5 V16 H1 A1 9 H1 XH2 B1 10 XH2 XH4 C1 11 XH4 $VBLW · -> 5M pin 1 Y2 6 $VBLW $H124 · -> 4M pin 12 & 4K pin 11 Y1 8 $H124 GND:7=GND VCC:14=+5V 3M — 74LS08: Clock-phase gates (latch/VRAM timing windows). All four units in the tangled corner - inputs/outputs on the review list — verified 2026-07-21 3M ✓ 74LS08 XH2 B1 1 XH2 H1 A1 2 H1 /$XH4 · <- 4K pin 8 A2 4 /$XH4 4-3H · <- 4N pin 9 (also CN-2 C4) B2 5 4-3H H256 B3 9 H256 /$H124 · <- 4K pin 10 A3 10 /$H124 /$H124 · <- 4K pin 10 B4 12 /$H124 /H256 · <- 4K pin 4 A4 13 /H256 $PH1Y · -> 4N pin 12 (D1) Y1 3 $PH1Y $PH2Y · -> 4N pin 2 (D2) Y2 6 $PH2Y $PH3Y · -> 3L pin 12 (K) Y3 8 $PH3Y $PH4Y · -> 3L pin 11 (J) Y4 11 $PH4Y GND:7=GND VCC:14=+5V 4K — 74LS04: Inverters in the phase/blanking decode (incl. the /$V128 inverter for the VBL window). Unit wiring on the review list — verified 2026-07-21 4K ✓ 74LS04 drawn on a2-6-charvram - click to jump there · H4 A1 1 H4 ↗ H256 A2 3 H256 V128 A3 5 V128 XH4 A4 9 XH4 $H124 · <- 4L pin 8 (shared with 4M pin 12) A5 11 $H124 drawn on a2-6-charvram - click to jump there · /$H4C · -> 7J/7K/6K SEL (pin1) + 6F pin 12 Y1 2 /$H4C ↗ /H256 · -> 3M pin 13 Y2 4 /H256 /$V128 Y3 6 /$V128 /$XH4 · -> 3M pin 4 Y4 8 /$XH4 /$H124 · -> 3M pins 10 & 12 Y5 10 /$H124 GND:7=GND VCC:14=+5V 4M — 74LS74: Phase FF pair generating OH. Unit 1 samples $H124 (the end-of-line decode from 4L pin 8) on L6M; unit 2 re-times it on X6M and its /Q (pin 6) is OH - the once-per-line row-latch clock, sent out to sheet 6/8 and to CN-2 D3 for the B and C boards, and used locally to clock 5M. — verified 2026-07-21 4M ✓ 74LS74 +5V ~CL2 1 +5V $PHM1Q · D2 <- own Q1 (pin 9) D2 2 $PHM1Q X6M · clk (shared with 4N pin 3) CLK2 3 X6M +5V ~PR2 4 +5V +5V ~PR1 10 +5V L6M · clk (shared with 3L pin 13) CLK1 11 L6M $H124 · <- 4L pin 8, shared with 4K pin 11 D1 12 $H124 +5V ~CL1 13 +5V OH · joined 2026-07-27: the sheet labels 4M pin 6 OH in both places (out to 6/8 and to CN-2 D3); PHM2NQ was our invented name, so the driver never joined its consumers ~Q2 6 OH $PHM1Q · Q1 -> 4M pin 2 (D2) only Q1 9 $PHM1Q GND:7=GND VCC:14=+5V 4N — 74LS74: Phase FF pair (L6M/X6M-clocked): FF-1 samples 3M $PH1Y -> 4-3H (CN-2 C4); FF-2 samples 3M $PH2Y -> 4H (CN-2 D4). Both feed back into 3M gate inputs. (H1/PhiB generation is elsewhere.) — verified 2026-07-21 4N ✓ 74LS74 +5V ~CL2 1 +5V $PH2Y · D2 <- 3M pin 6 D2 2 $PH2Y X6M · clk (same as 4M pin 3) CLK2 3 X6M +5V ~PR2 4 +5V +5V ~PR1 10 +5V L6M · from 2M pin 5 CLK1 11 L6M $PH1Y · D1 <- 3M pin 3 D1 12 $PH1Y +5V ~CL1 13 +5V 4H · Q2 -> CN-2 D4 Q2 5 4H 4-3H · -> CN-2 C4 and 3M pin 5 Q1 9 4-3H GND:7=GND VCC:14=+5V
· Original scan — manual p27 · zoom
original schematic scan
2N
2M
3K
2K
1K
1M
2L
1L
3N
5L
5N
5M
5K
3L
4L
3M
4K
4M
4N