85605-A-2 Sheet 6/8 — CHARACTER VIDEO RAM

manual p28 · 18 ICs · 18 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Interboard connectors (the band cables between the boards) — circled letter+number labels on the drawing are connector row + pin
5J — 74LS86: Flip XOR pack (FLIP on 2/5/10/13): g1 V8->V8F($CA5), g2 H128->H128F($CA4), g3 V16->V16F($CA6), g4 V32->V32F($CA7) — verified 2026-07-25 5J ✓ 74LS86 V8 A1 1 V8 $CFLIP · <- 4J pin 11 (distributed flip) B1 2 $CFLIP H128 · H128 -> pin 6 -> 7K pin 10 ($CA4) A2 4 H128 $CFLIP · <- 4J pin 11 (distributed flip) B2 5 $CFLIP V16 A3 9 V16 $CFLIP · <- 4J pin 11 (distributed flip) B3 10 $CFLIP V32 A4 12 V32 $CFLIP · <- 4J pin 11 (distributed flip) B4 13 $CFLIP V8F · -> 7K.13 ($CA5) Y1 3 V8F H128F · -> 7K.10 ($CA4) Y2 6 H128F V16F · -> 7K.6 ($CA6) Y3 8 V16F V32F · -> 7K.3 ($CA7) Y4 11 V32F GND:7=GND VCC:14=+5V 6J — 74LS86: Flip XOR pack (FLIP on 2/5/10/13): g1 H32->H32F($CA2), g2 V64->V64F($CA8), g3 V128->V128F($CA9), g4 H8->H8F($CA0) — verified 2026-07-25 6J ✓ 74LS86 H32 A1 1 H32 $CFLIP · <- 4J pin 11 (distributed flip) B1 2 $CFLIP V64 A2 4 V64 $CFLIP · <- 4J pin 11 (distributed flip) B2 5 $CFLIP V128 A3 9 V128 $CFLIP · <- 4J pin 11 (distributed flip) B3 10 $CFLIP H8 A4 12 H8 $CFLIP · <- 4J pin 11 (distributed flip) B4 13 $CFLIP H32F · -> 7J.3 ($CA2) Y1 3 H32F V64F · -> 6K.6 ($CA8) Y2 6 V64F V128F · -> 6K.10 ($CA9) Y3 8 V128F H8F · -> 7J.13 ($CA0) Y4 11 H8F GND:7=GND VCC:14=+5V 4J — 74LS86: Flip XORs + FLIP buffer: g2 H16->H16F($CA1), g3 H64->H64F($CA3), g4 = FLIP(2/8) XOR GND -> $CFLIP distributed to all three 86 flip inputs. g1 spare — verified 2026-07-25 4J ✓ 74LS86 H16 A2 4 H16 $CFLIP B2 5 $CFLIP H64 A3 9 H64 $CFLIP B3 10 $CFLIP FLIP · raw FLIP from 2/8 A4 12 FLIP GND B4 13 GND H16F · -> 7J.6 ($CA1) Y2 6 H16F H64F · -> 7J.10 ($CA3) Y3 8 H64F $CFLIP · buffered FLIP -> 4J/5J/6J flip inputs Y4 11 $CFLIP GND:7=GND VCC:14=+5V 7J — 74LS157: Char-VRAM address mux low, SEL=/$H4C (4K.2): A=CPU AB0-AB3->$CA0-$CA3 straight; B=display column H8F/H16F/H32F/H64F (from 4J/6J flip XORs) -> $CA0=H8,$CA1=H16,$CA2=H32,$CA3=H64. Out to 7F A0-A3 — verified 2026-07-25 7J ✓ 74LS157 /$H4C · <- 4K pin 2 (4K inverts H4) SEL 1 /$H4C AB2 A1 2 AB2 H32F · <- 6J pin 3 (H32 XOR FLIP) B1 3 H32F AB1 A2 5 AB1 H16F · <- 4J pin 6 (H16 XOR FLIP) B2 6 H16F H64F · <- 4J pin 8 (H64 XOR FLIP) B3 10 H64F AB3 A3 11 AB3 H8F · <- 6J pin 11 (H8 XOR FLIP) B4 13 H8F AB0 A4 14 AB0 GND ~ST 15 GND $CA2 · -> 7F pin 6 (A2) | bare on the drawing (Robert, 2026-07-27) - the CA name is ours Y1 4 $CA2 $CA1 · -> 7F pin 7 (A1) | bare on the drawing (Robert, 2026-07-27) - the CA name is ours Y2 7 $CA1 $CA3 · -> 7F pin 5 (A3) | bare on the drawing (Robert, 2026-07-27) - the CA name is ours Y3 9 $CA3 $CA0 · -> 7F pin 8 (A0) | bare on the drawing (Robert, 2026-07-27) - the CA name is ours Y4 12 $CA0 GND:8=GND VCC:16=+5V 7K — 74LS157: Char-VRAM address mux mid, SEL=/$H4C: A=CPU AB4-AB7->$CA4-$CA7 straight; B=display ROW V8F/V16F/V32F/V64F (from 5J flip XORs): $CA4=V8,$CA5=V16,$CA6=V32,$CA7=V64. Out to 7F A4-A7 — verified 2026-07-25 7K ✓ 74LS157 /$H4C · <- 4K pin 2 SEL 1 /$H4C AB7 A1 2 AB7 V32F · <- 5J pin 11 -> $CA7 (V32) B1 3 V32F AB6 · (read as AB6; you said AB5) A2 5 AB6 V16F · <- 5J pin 8 -> $CA6 (V16) B2 6 V16F H128F · <- 5J pin 6 -> $CA4 (H128) B3 10 H128F AB4 A3 11 AB4 V8F · <- 5J pin 3 -> $CA5 (V8) B4 13 V8F AB5 A4 14 AB5 GND ~ST 15 GND $CA7 · -> 7F pin 1 (A7) | bare on the drawing (Robert, 2026-07-27) - the CA name is ours Y1 4 $CA7 $CA6 · -> 7F pin 2 (A6) | bare on the drawing (Robert, 2026-07-27) - the CA name is ours Y2 7 $CA6 $CA4 · -> 7F pin 4 (A4) | bare on the drawing (Robert, 2026-07-27) - the CA name is ours Y3 9 $CA4 $CA5 · -> 7F pin 3 (A5) | bare on the drawing (Robert, 2026-07-27) - the CA name is ours Y4 12 $CA5 GND:8=GND VCC:16=+5V 6K — 74LS157: Char-VRAM addr mux high + OE switch, SEL=/$H4C: A=CPU AB8/AB9/AB10->$CA8/CA9/CA10; B=display $CA8=H128F,$CA9=V128F (6J), $CA10=H2C. 4th sect: /$CHOE = /RDB (CPU) vs GND (display) -> 7F OE — verified 2026-07-25 6K ✓ 74LS157 /$H4C · <- 4K pin 2 SEL 1 /$H4C AB10 A1 2 AB10 H2 · display $CA10 (you read H2) = code/attr toggle | joined 2026-07-27: arrives from 5/8 3K pin 13, not a locally-made variant B1 3 H2 AB8 · you said pin 9 - read as pin 5 -> $CA8 A2 5 AB8 V64F · <- 6J pin 6 -> $CA8 (V64) B2 6 V64F V128F · <- 6J pin 8 -> $CA9 B3 10 V128F AB9 A3 11 AB9 GND · display: VRAM OE grounded (always on) B4 13 GND /RDB · <- 1/8; also 6H.1 + 3F.1 (VRAM OE follows /RDB on CPU read) A4 14 /RDB GND ~ST 15 GND $CA10 · -> 7F pin 19 (A10) | bare on the drawing (Robert, 2026-07-27) - the CA name is ours Y1 4 $CA10 $CA8 · -> 7F pin 23 (A8) | bare on the drawing (Robert, 2026-07-27) - the CA name is ours Y2 7 $CA8 $CA9 · -> 7F pin 22 (A9) | bare on the drawing (Robert, 2026-07-27) - the CA name is ours Y3 9 $CA9 /$CHOE · -> 7F pin 20 (OE) Y4 12 /$CHOE GND:8=GND VCC:16=+5V 7F — M58725: 2kB char VRAM (D000-D3FF code, D400-D7FF attributes). Always chip-enabled; /WE from the 3F write gate — verified 2026-07-25 7F ✓ M58725 $CA7 · bare on the drawing (Robert, 2026-07-27) - the CA name is ours A7 1 $CA7 $CA6 · bare on the drawing (Robert, 2026-07-27) - the CA name is ours A6 2 $CA6 $CA5 · bare on the drawing (Robert, 2026-07-27) - the CA name is ours A5 3 $CA5 $CA4 · bare on the drawing (Robert, 2026-07-27) - the CA name is ours A4 4 $CA4 $CA3 · bare on the drawing (Robert, 2026-07-27) - the CA name is ours A3 5 $CA3 $CA2 · bare on the drawing (Robert, 2026-07-27) - the CA name is ours A2 6 $CA2 $CA1 · bare on the drawing (Robert, 2026-07-27) - the CA name is ours A1 7 $CA1 $CA0 · bare on the drawing (Robert, 2026-07-27) - the CA name is ours A0 8 $CA0 DC0 D0 9 DC0 DC1 D1 10 DC1 DC2 D2 11 DC2 DC3 D3 13 DC3 DC4 D4 14 DC4 DC5 D5 15 DC5 DC6 D6 16 DC6 DC7 D7 17 DC7 GND · ~CE always GND ~CE 18 GND $CA10 · bare on the drawing (Robert, 2026-07-27) - the CA name is ours A10 19 $CA10 /$CHOE · ~OE <- 6K pin 12 /$CHOE ~OE 20 /$CHOE /$CHWE · ~WE <- 3F pin 3 /$CHWE ~WE 21 /$CHWE $CA9 · bare on the drawing (Robert, 2026-07-27) - the CA name is ours A9 22 $CA9 $CA8 · bare on the drawing (Robert, 2026-07-27) - the CA name is ours A8 23 $CA8 GND:12=GND VCC:24=+5V 3F — 74LS00: Char RAM write gate: /$CHWE = NAND(/RDB, 4H.9) -> 7F ~WE (write when not reading + FF grant) — verified 2026-07-25 3F ✓ 74LS00 /RDB · <- 1/8 (also 6H.1, 6K.14) A1 1 /RDB $CHWGATE · <- 4H pin 9 B1 2 $CHWGATE drawn on a2-8-colormixer - click to jump there · LHBL · <- 5/8 (horizontal blanking) A3 9 LHBL ↗ drawn on a2-8-colormixer - click to jump there · LVBL · <- 5/8 (vertical blanking) B3 10 LVBL ↗ drawn on a2-8-colormixer - click to jump there · CHARA · <- 1F pin 2 A4 12 CHARA ↗ drawn on a2-8-colormixer - click to jump there · CHARB · <- 1F pin 15 B4 13 CHARB ↗ /$CHWE · -> 7F pin 21 (~WE) Y1 3 /$CHWE drawn on a2-8-colormixer - click to jump there · /$BLANK · -> 1E pin 12 (D2): resampled before clearing 2E Y3 8 /$BLANK ↗ drawn on a2-8-colormixer - click to jump there · /$CHTRANS · -> 1H pin 6 (A1) + 2F/2H/2J pin 2 (B select) Y4 11 /$CHTRANS ↗ GND:7=GND VCC:14=+5V 6H — 74LS245: CPU window into the char RAM: DB bus <-> DC bus (the repaired 6H from Fixes.txt). DIR = /RDB — verified 2026-07-25 6H ✓ 74LS245 /RDB · DIR <- /RDB (1/8): read=DC->DB, write=DB->DC DIR 1 /RDB DB6 A1 2 DB6 DB5 A2 3 DB5 DB4 A3 4 DB4 DB3 A4 5 DB3 DB2 A5 6 DB2 DB1 A6 7 DB1 DB7 A7 8 DB7 DB0 A8 9 DB0 DC0 B8 11 DC0 DC7 B7 12 DC7 DC1 B6 13 DC1 DC2 B5 14 DC2 DC3 B4 15 DC3 DC4 B3 16 DC4 DC5 B2 17 DC5 DC6 B1 18 DC6 /$CHEN · ~G <- 4H pin 8 (access-grant FF); same net also -> 6F pin 9 ~G 19 /$CHEN GND:10=GND VCC:20=+5V 6E — 74LS273: Code-byte pipeline stage 1: DC0-DC7 latched at the 4H phase — verified 2026-07-25 6E ✓ 74LS273 +5V ~CL 1 +5V DC3 D1 3 DC3 DC2 D2 4 DC2 DC1 D3 7 DC1 DC0 D4 8 DC0 $CHLD · CLK <- 6F pin 11 (display fetch strobe) CLK 11 $CHLD DC7 D5 13 DC7 DC6 D6 14 DC6 DC5 D7 17 DC5 DC4 D8 18 DC4 $CP3 Q1 2 $CP3 $CP2 Q2 5 $CP2 $CP1 Q3 6 $CP1 $CP0 Q4 9 $CP0 $CP7 Q5 12 $CP7 $CP6 Q6 15 $CP6 $CP5 Q7 16 $CP5 $CP4 Q8 19 $CP4 GND:10=GND VCC:20=+5V 6D — 74LS273: Code-byte pipeline stage 2 -> AC0-AC7 to the char generator (7/8) — verified 2026-07-25 6D ✓ 74LS273 +5V ~CL 1 +5V $CP0 D1 3 $CP0 $CP1 D2 4 $CP1 $CP2 D3 7 $CP2 $CP3 D4 8 $CP3 4H · CLK <- 4H phase CLK 11 4H $CP4 D5 13 $CP4 $CP5 D6 14 $CP5 $CP6 D7 17 $CP6 $CP7 D8 18 $CP7 AC0 Q1 2 AC0 AC1 Q2 5 AC1 AC2 Q3 6 AC2 AC3 Q4 9 AC3 AC4 Q5 12 AC4 AC5 Q6 15 AC5 AC6 Q7 16 AC6 AC7 Q8 19 AC7 GND:10=GND VCC:20=+5V 7E — 74LS273: Attribute latch (CLK 4H): DC0-DC3->$CCL0-$CCL3 (colour, ->7D), DC6/DC7->AC8/AC9 (code high bits), DC5->CHVFLIP, DC4->CHHFLIP (->7D.11) — verified 2026-07-25 7E ✓ 74LS273 +5V ~CL 1 +5V DC3 D1 3 DC3 DC2 D2 4 DC2 DC1 D3 7 DC1 DC0 D4 8 DC0 4H · CLK <- 4H phase CLK 11 4H DC7 D5 13 DC7 DC6 D6 14 DC6 DC5 D7 17 DC5 DC4 D8 18 DC4 $CCL3 · -> 7D.6 Q1 2 $CCL3 $CCL2 · -> 7D.4 Q2 5 $CCL2 $CCL1 · -> 7D.3 Q3 6 $CCL1 $CCL0 · -> 7D.14 Q4 9 $CCL0 AC9 Q5 12 AC9 AC8 Q6 15 AC8 CHVFLIP · to 7/8 Q7 16 CHVFLIP CHHFLIP · CHHFLIP -> 7D.11 Q8 19 CHHFLIP GND:10=GND VCC:20=+5V 7D — 74LS174: Color-code latch at OH: CC0-CC3 to the palette (8/8) + CHHFLIPa (re-latched flip, alpha-suffix pattern like the C board). Pin 2 = the dirty-board stuck-high repair — verified 2026-07-25 7D ✓ 74LS174 +5V ~CL 1 +5V $CCL1 D1 3 $CCL1 $CCL2 D2 4 $CCL2 $CCL3 D3 6 $CCL3 OH · CLK <- OH (from 5/8) CLK 9 OH CHHFLIP D4 11 CHHFLIP $CCL0 D6 14 $CCL0 CC1 · to 8/8 - the 74LS174 first-FF stuck-high colour repair Q1 2 CC1 CC2 · to 8/8 Q2 5 CC2 CC3 · to 8/8 Q3 7 CC3 CHHFLIPa · to 7/8 Q4 10 CHHFLIPa CC0 · to 8/8 Q6 15 CC0 GND:8=GND VCC:16=+5V 4K — 74LS04: H4 inverter: gate1 H4 -> /$H4C (mux SELs 7J/7K/6K + 6F.12). Gates 2-5 are drawn on sheet 5/8 (same physical 74LS04 at 4K); gate 6 (pins 13->12) is unused - no tracks on the board. — verified 2026-07-25 4K ✓ 74LS04 H4 A1 1 H4 drawn on a2-5-sync - click to jump there · H256 A2 3 H256 ↗ drawn on a2-5-sync - click to jump there · V128 A3 5 V128 ↗ drawn on a2-5-sync - click to jump there · XH4 A4 9 XH4 ↗ drawn on a2-5-sync - click to jump there · $H124 · <- 4L pin 8 (shared with 4M pin 12) A5 11 $H124 ↗ /$H4C · -> 7J/7K/6K SEL (pin1) + 6F pin 12 Y1 2 /$H4C drawn on a2-5-sync - click to jump there · /H256 · -> 3M pin 13 Y2 4 /H256 ↗ drawn on a2-5-sync - click to jump there · /$V128 Y3 6 /$V128 ↗ drawn on a2-5-sync - click to jump there · /$XH4 · -> 3M pin 4 Y4 8 /$XH4 ↗ drawn on a2-5-sync - click to jump there · /$H124 · -> 3M pins 10 & 12 Y5 10 /$H124 ↗ GND:7=GND VCC:14=+5V 6F — 74LS08: Arbitration gates: g4 /$H4C*H2 -> $CHLD (6E clock, display fetch strobe); g3 /$CHEN*DOCS -> 4H pin1 ~CL (ends CPU grant). Gates 1-2 not drawn on this sheet. Gate 2 (pins 4,5->6) is unused: drawn on neither 3/8 nor 6/8 and no tracks on the board. — verified 2026-07-25 6F ✓ 74LS08 drawn on a2-3-sound - click to jump there · /$SC23 · <- 10E pin 14 A1 1 /$SC23 ↗ drawn on a2-3-sound - click to jump there · /$SC01 · <- 10E pin 15 B1 2 /$SC01 ↗ /$CHEN · <- 4H pin 8 B3 9 /$CHEN $D0CS · <- 3E pin 6 | renamed 2026-07-27: same net as io 3B pin 6 /$D0CS (D000-D7FF) - was a letter-O vs zero split A3 10 $D0CS /$H4C · <- 4K pin 2 B4 12 /$H4C H2 · H2 display | joined 2026-07-27: arrives from 5/8 3K pin 13, not a locally-made variant A4 13 H2 drawn on a2-3-sound - click to jump there · /$SROMCE · /$SROMCE low for 0000-3FFF -> 9F ~CE Y1 3 /$SROMCE ↗ $ARBCL · -> 4H pin 1 ~CL (ends CPU grant) Y3 8 $ARBCL $CHLD · -> 6E CLK (display fetch strobe) Y4 11 $CHLD GND:7=GND VCC:14=+5V 3E — 74LS04: Inverts /DOCS (D000-D7FF char window, from 2/8) -> DOCS to the arbitration (6F.10, 4H.13) — verified 2026-07-25 3E ✓ 74LS04 drawn on a2-7-chargen - click to jump there · CHHFLIPa · <- 7D pin 10 (sheet 6) raw char h-flip A 1 CHHFLIPa ↗ /D0CS · char window D000-D7FF select from 2/8 | renamed 2026-07-27: same net as io 3B pin 6 /$D0CS (D000-D7FF) - was a letter-O vs zero split A3 5 /D0CS drawn on a2-8-colormixer - click to jump there · CH6M · <- 7/8 pixel clock A 13 CH6M ↗ drawn on a2-7-chargen - click to jump there · /$CHHFLIP · -> 4C pin 4 Y 2 /$CHHFLIP ↗ $D0CS · -> 6F pin 10 + 4H pin 13 | renamed 2026-07-27: same net as io 3B pin 6 /$D0CS (D000-D7FF) - was a letter-O vs zero split Y3 6 $D0CS drawn on a2-8-colormixer - click to jump there · /$CH6M · output is not lettered on the sheet; /$CH6M is our name (Robert confirmed the gate itself, 2026-07-27) Y 12 /$CH6M ↗ GND:7=GND VCC:14=+5V 5H — 74LS32: Gated main CPU clock: g3 (9,10->8) PHISC(<-CN-1 B15) OR grant(4H.5) -> $PHIW; g2 (4,5->6) PHIB(sync) OR $PHIW -> PHIMAIN out to CPU 1/8. Clock-stretch wait during char-RAM contention. Gates 1&4 spare. — verified 2026-07-25 5H ✓ 74LS32 PHIB · <- sync 5/8 (phi-B) A2 4 PHIB $PHIW · <- 5H pin 8 (feedback) B2 5 $PHIW PHISC · <- CN-1 B15 (from C board / screen timing) A3 9 PHISC $ARBQ1 · <- 4H pin 5 (grant FF Q1) B3 10 $ARBQ1 drawn on a2-7-chargen - click to jump there · 6M · <- 5/8 (6MHz pixel clock) A4 12 6M ↗ drawn on a2-7-chargen - click to jump there · GND · tied GND (OR = buffer) B4 13 GND ↗ PHIMAIN · -> CPU sheet 1/8: gated main clock = PHIB OR $PHIW Y2 6 PHIMAIN $PHIW · g3 out = PHISC OR grant -> 5H pin 5 Y3 8 $PHIW drawn on a2-7-chargen - click to jump there · CH6M · -> 4F/5F pin 11 (CLK) + to 8/8 Y4 11 CH6M ↗ GND:7=GND VCC:14=+5V 4H — 74LS74: Access-grant sync: unit2 (CLK 4H, D=+5, ~CL=DOCS) -> ~Q2=/$CHEN (6H enable) + Q2 (3F write gate); unit1 (CLK phi-B, D=+5, ~CL=6F.8 $ARBCL) -> Q1 to 5H (PHISC gen) — verified 2026-07-25 4H ✓ 74LS74 $ARBCL · <- 6F pin 8 ~CL1 1 $ARBCL +5V D1 2 +5V PHIB · <- 5/8 (phi-B) CLK1 3 PHIB +5V ~PR1 4 +5V +5V ~PR2 10 +5V 4H · <- 4H phase CLK2 11 4H +5V D2 12 +5V $D0CS · <- 3E pin 6 (char window) | renamed 2026-07-27: same net as io 3B pin 6 /$D0CS (D000-D7FF) - was a letter-O vs zero split ~CL2 13 $D0CS $ARBQ1 · -> 5H pin 10 (PHISC gen) Q1 5 $ARBQ1 /$CHEN · ~Q2 -> 6H pin 19 (/$CHEN enable) + 6F pin 9 ~Q2 8 /$CHEN $CHWGATE · Q2 -> 3F pin 2 (write gate with /RDB -> /$CHWE) Q2 9 $CHWGATE GND:7=GND VCC:14=+5V
· Original scan — manual p28 · zoom
original schematic scan
5J
6J
4J
7J
7K
6K
7F
3F
6H
6E
6D
7E
7D
4K
6F
3E
5H
4H