85605-A-2 Sheet 7/8 — CHARACTER GENERATOR ROM

manual p29 · 9 ICs · 9 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
4E — 74LS174: Row-bit latch (174): D1=V4,D5=V1,D6=V2 registered on the 4H phase (CLK pin 9); H4 is a separate line feeding 4D pin 2 -> $CGV4L/CGV1L/CGV2L to 4D flip XORs (pins 4/12/9). ~CL=+5. FFs 2/3/4 unused. — verified 2026-07-25 4E ✓ 74LS174 +5V ~CL 1 +5V V4 D1 3 V4 4H · CLK <- 4H phase (CN-2 D4 net, from 5/8 4N pin 5). CORRECTED 2026-07-27: was wrongly recorded as H4; the drawing shows 4H and H4 as separate lines in the same bundle CLK 9 4H V1 D5 13 V1 V2 D6 14 V2 $CGV4L · -> 4D pin 4 Q1 2 $CGV4L $CGV1L · -> 4D pin 12 Q5 12 $CGV1L $CGV2L · -> 4D pin 9 Q6 15 $CGV2L GND:8=GND VCC:16=+5V 4D — 74LS86: Char ROM row-address XORs: $CGA0=H4^$CHHCORR (5D A0); $CGA1=$CGV1L^$CHVCORR (A1); $CGA2=$CGV2L^$CHVCORR (A2); $CGA3=$CGV4L^$CHVCORR (A3). Row bits from 4E latch, flip corrections from 4C. — verified 2026-07-25 4D ✓ 74LS86 $CHHCORR · <- 4C pin 6 B1 1 $CHHCORR H4 · <- H4 (CN-2 C6 net, from 5/8 3K pin 5) - a DIFFERENT signal from the 4H clocking 4E A1 2 H4 $CGV4L · <- 4E pin 2 A2 4 $CGV4L $CHVCORR · <- 4C pin 8 B2 5 $CHVCORR $CGV2L · <- 4E pin 15 A3 9 $CGV2L $CHVCORR · <- 4C pin 8 B3 10 $CHVCORR $CGV1L · <- 4E pin 12 A4 12 $CGV1L $CHVCORR · <- 4C pin 8 B4 13 $CHVCORR $CGA0 · -> 5D pin 10 (A0) Y1 3 $CGA0 $CGA3 · -> 5D pin 7 (A3) Y2 6 $CGA3 $CGA2 · -> 5D pin 8 (A2) Y3 8 $CGA2 $CGA1 · -> 5D pin 9 (A1) Y4 11 $CGA1 GND:7=GND VCC:14=+5V 4C — 74LS86: Flip-control XORs: g1 buffers FLIP->$CGFLIP; g2 (/$CHHFLIP^$CGFLIP)->$CHHCORR to 4D.1; g3 (CHVFLIP^$CGFLIP)->$CHVCORR to 4D.5/10/13; g4 (CHHFLIPa^$CGFLIP)->$CHHSEL to 3H.1 SEL — verified 2026-07-25 4C ✓ 74LS86 FLIP · <- 2/8 io control reg (7A DB7) A1 1 FLIP GND · tied GND (XOR = buffer) B1 2 GND /$CHHFLIP · <- 3E pin 2 (/$CHHFLIP inverted) A2 4 /$CHHFLIP $CGFLIP · <- 4C pin 3 B2 5 $CGFLIP CHVFLIP · <- 6/8 char attribute latch A3 9 CHVFLIP $CGFLIP · <- 4C pin 3 B3 10 $CGFLIP $CGFLIP · <- 4C pin 3 A4 12 $CGFLIP CHHFLIPa · <- 7D pin 10 (sheet 6) raw char h-flip B4 13 CHHFLIPa $CGFLIP · FLIP buffered -> 4C pins 5,10,12 Y1 3 $CGFLIP $CHHCORR · -> 4D pin 1 (H-flip corr for $CGA0/H4 term) Y2 6 $CHHCORR $CHVCORR · -> 4D pins 5,10,13 (V-flip corr). NOTE Robert read pin 14 but that is 4D VCC -> used 13; confirm Y3 8 $CHVCORR $CHHSEL · -> 3H pin 1 SEL (pixel-shift direction) Y4 11 $CHHSEL GND:7=GND VCC:14=+5V 3E — 74LS04: /$CHHFLIP inverter (04): CHHFLIPa (7D.10 sheet 6) -> /$CHHFLIP -> 4C pin 4. Shared 04 package (other gate = /DOCS on sheet 6). — verified 2026-07-25 3E ✓ 74LS04 CHHFLIPa · <- 7D pin 10 (sheet 6) raw char h-flip A 1 CHHFLIPa drawn on a2-6-charvram - click to jump there · /D0CS · char window D000-D7FF select from 2/8 | renamed 2026-07-27: same net as io 3B pin 6 /$D0CS (D000-D7FF) - was a letter-O vs zero split A3 5 /D0CS ↗ drawn on a2-8-colormixer - click to jump there · CH6M · <- 7/8 pixel clock A 13 CH6M ↗ /$CHHFLIP · -> 4C pin 4 Y 2 /$CHHFLIP drawn on a2-6-charvram - click to jump there · $D0CS · -> 6F pin 10 + 4H pin 13 | renamed 2026-07-27: same net as io 3B pin 6 /$D0CS (D000-D7FF) - was a letter-O vs zero split Y3 6 $D0CS ↗ drawn on a2-8-colormixer - click to jump there · /$CH6M · output is not lettered on the sheet; /$CH6M is our name (Robert confirmed the gate itself, 2026-07-27) Y 12 /$CH6M ↗ GND:7=GND VCC:14=+5V 5H — 74LS32: Gate 4 of the shared 32 package (other gates on 6/8 make PHIMAIN): 6M OR GND = buffered CH6M pixel clock -> 4F/5F shifter CLK and to 8/8. — verified 2026-07-25 5H ✓ 74LS32 drawn on a2-6-charvram - click to jump there · PHIB · <- sync 5/8 (phi-B) A2 4 PHIB ↗ drawn on a2-6-charvram - click to jump there · $PHIW · <- 5H pin 8 (feedback) B2 5 $PHIW ↗ drawn on a2-6-charvram - click to jump there · PHISC · <- CN-1 B15 (from C board / screen timing) A3 9 PHISC ↗ drawn on a2-6-charvram - click to jump there · $ARBQ1 · <- 4H pin 5 (grant FF Q1) B3 10 $ARBQ1 ↗ 6M · <- 5/8 (6MHz pixel clock) A4 12 6M GND · tied GND (OR = buffer) B4 13 GND drawn on a2-6-charvram - click to jump there · PHIMAIN · -> CPU sheet 1/8: gated main clock = PHIB OR $PHIW Y2 6 PHIMAIN ↗ drawn on a2-6-charvram - click to jump there · $PHIW · g3 out = PHISC OR grant -> 5H pin 5 Y3 8 $PHIW ↗ CH6M · -> 4F/5F pin 11 (CLK) + to 8/8 Y4 11 CH6M GND:7=GND VCC:14=+5V 5D — 27128: Character generator ROM (27128). A4-A13 = char code AC0-AC9 (from 6/8); A0-A3 = row address $CGA0-$CGA3 (from 4D flip XORs). ~CE(20)/~OE(22)/GND(14) to GND - permanently enabled; VPP(1)/~PGM(27)/VCC(28) to +5. D0-D3 = $CY0-3 -> 5F (Y plane); D4-D7 = $CZ0-3 -> 4F (Z plane). — verified 2026-07-25 5D ✓ 27128 AC8 · AC8 A12 2 AC8 AC3 · AC3 A7 3 AC3 AC2 · AC2 A6 4 AC2 AC1 · AC1 A5 5 AC1 AC0 · AC0 A4 6 AC0 $CGA3 · $CGA3 <- 4D pin 6 A3 7 $CGA3 $CGA2 · $CGA2 <- 4D pin 8 A2 8 $CGA2 $CGA1 · $CGA1 <- 4D pin 11 A1 9 $CGA1 $CGA0 · $CGA0 <- 4D pin 3 A0 10 $CGA0 GND · ~CE tied GND (always enabled) ~CE 20 GND AC6 · AC6 A10 21 AC6 GND · ~OE tied GND (always enabled) ~OE 22 GND AC7 · AC7 A11 23 AC7 AC5 · AC5 A9 24 AC5 AC4 · AC4 A8 25 AC4 AC9 · AC9 A13 26 AC9 $CY0 · -> 5F (Y plane, low nibble) D0 11 $CY0 $CY1 · -> 5F D1 12 $CY1 $CY2 · -> 5F D2 13 $CY2 $CY3 · -> 5F D3 15 $CY3 $CZ0 · -> 4F (Z plane, high nibble) D4 16 $CZ0 $CZ1 · -> 4F D5 17 $CZ1 $CZ2 · -> 4F D6 18 $CZ2 $CZ3 · -> 4F D7 19 $CZ3 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 4F — 74LS194A: Z-plane pixel shifter (194): loads $CZ0-3 (5D D4-D7) when 4-3H high, then shifts left (normal) or right (flipped) per $CHS0/CHS1 from 3H. QA+QD -> 3H group 1 -> CHARZ. — verified 2026-07-25 4F ✓ 74LS194A +5V ~CL 1 +5V GND · shift-right serial in tied GND SR 2 GND $CZ3 A 3 $CZ3 $CZ2 B 4 $CZ2 $CZ1 C 5 $CZ1 $CZ0 D 6 $CZ0 GND · shift-left serial in tied GND SL 7 GND $CHS0 · <- 3H pin 12 (4Y) S0 9 $CHS0 $CHS1 · <- 3H pin 9 (3Y) S1 10 $CHS1 CH6M · <- 5H pin 11 CLK 11 CH6M $CZQD · -> 3H pin 6 (flip direction) QD 12 $CZQD $CZQA · -> 3H pin 5 (1A, normal direction) QA 15 $CZQA GND:8=GND VCC:16=+5V 5F — 74LS194A: Y-plane pixel shifter (194): loads $CY0-3 (5D D0-D3) when 4-3H high, then shifts per $CHS0/CHS1 from 3H. QA(15)->3H pin 2, QD(12)->3H pin 3 -> CHARY. — verified 2026-07-25 5F ✓ 74LS194A +5V ~CL 1 +5V GND · shift-right serial in tied GND SR 2 GND $CY3 A 3 $CY3 $CY2 B 4 $CY2 $CY1 C 5 $CY1 $CY0 D 6 $CY0 GND · shift-left serial in tied GND SL 7 GND $CHS0 · <- 3H pin 12 (4Y) S0 9 $CHS0 $CHS1 · <- 3H pin 9 (3Y) S1 10 $CHS1 CH6M · <- 5H pin 11 CLK 11 CH6M $CYQD · -> 3H pin 3 (2B) QD 12 $CYQD $CYQA · -> 3H pin 2 (2A) QA 15 $CYQA GND:8=GND VCC:16=+5V 3H — 74LS157: Quad 2-to-1 mux (157), SEL=$CHHSEL. Groups 1&2 pick pixel-shift direction: QA (normal) vs QD (flipped) -> CHARZ (pin7) / CHARY (pin4). Groups 3&4 build the shifter mode: $CHS1=(+5 / 4-3H), $CHS0=(4-3H / +5) so both shifters load on 4-3H then shift left (normal) or right (flipped). — verified 2026-07-25 3H ✓ 74LS157 $CHHSEL · <- 4C pin 11 (per-char h-flip XOR global FLIP) SEL 1 $CHHSEL $CYQA · <- 5F pin 15 QA 2A 2 $CYQA $CYQD · <- 5F pin 12 QD 2B 3 $CYQD $CZQA · <- 4F QA (normal) 1A 5 $CZQA $CZQD · <- 4F QD (flipped) 1B 6 $CZQD 4-3H · <- 4N pin 9 (sync) 3B 10 4-3H +5V 3A 11 +5V +5V 4B 13 +5V 4-3H · <- 4N pin 9 (sync) 4A 14 4-3H GND · strobe tied GND - always enabled ~G 15 GND CHARY · -> 8/8 colour mixer 2Y 4 CHARY CHARZ · -> 8/8 colour mixer 1Y 7 CHARZ $CHS1 · -> 4F/5F pin 10 (S1) 3Y 9 $CHS1 $CHS0 · -> 4F/5F pin 9 (S0) 4Y 12 $CHS0 GND:8=GND VCC:16=+5V
· Original scan — manual p29 · zoom
original schematic scan
4E
4D
4C
3E
5H
5D
4F
5F
3H