85605-A-2 Sheet 8/8 — COLOR MIXER

manual p30 · 13 ICs · 13 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Interboard connectors (the band cables between the boards) — circled letter+number labels on the drawing are connector row + pin
1F — 74LS174: Char pixel/colour latch (174) clocked /$CH6M, ~CL=+5. In: CHARZ(3)/CHARY(14) from 3H sheet 7, CC0-CC3 (6,11,13,4) from 6/8. Out CHARA(2)/CHARB(15) = pixel bits (also feed 3F transparency NAND), CHARC(7)/CHARD(10)/CHARE(12)/CHARF(5) = colour code to the source muxes. — verified 2026-07-25 1F ✓ 74LS174 +5V ~CL 1 +5V CHARZ · <- 3H pin 7 (sheet 7) D1 3 CHARZ CC3 · <- CC3 (6/8) D2 4 CC3 CC0 · <- CC0 (6/8) D3 6 CC0 CH6M CLK 9 CH6M CC1 · <- CC1 (6/8) D4 11 CC1 CC2 · <- CC2 (6/8) D5 13 CC2 CHARY · <- 3H pin 4 (sheet 7) D6 14 CHARY CHARA · -> 3F pin 12 + 2F/2H/2J CHAR inputs Q1 2 CHARA CHARF Q2 5 CHARF CHARC Q3 7 CHARC CHARD Q4 10 CHARD CHARE Q5 12 CHARE CHARB · -> 3F pin 13 + mux CHAR inputs Q6 15 CHARB GND:8=GND VCC:16=+5V 3J — 74LS20: Sprite transparency detect (20, 4-input NAND): OBJA(10) OBJB(9) OBJC(12) OBJD(13) from B-board 1M. All four high = pen 15 = transparent -> pin 8 low. /$OBJTRANS -> 1H A0 + mux A-selects. Second gate of the package not drawn on this sheet. — verified 2026-07-25 3J ✓ 74LS20 OBJB · <- b1-5-linebuffer1 1M (B board, via band cable) B 9 OBJB OBJA · <- b1-5-linebuffer1 1M (B board, via band cable) A 10 OBJA OBJC · <- b1-5-linebuffer1 1M (B board, via band cable) C 12 OBJC OBJD · <- b1-5-linebuffer1 1M (B board, via band cable) D 13 OBJD /$OBJTRANS · -> 1H pin 5 (A0) + 2F/2H/2J pin 14 (A select) Y 8 /$OBJTRANS GND:7=GND VCC:14=+5V 3F — 74LS00: Two gates of the 00 on this sheet: g3 (9,10->8) LHBL NAND LVBL = /$BLANK -> 1E pin 12; g4 (12,13->11) CHARA NAND CHARB = /$CHTRANS (char pen 3 = transparent) -> 1H A1 + mux B-selects. — verified 2026-07-25 3F ✓ 74LS00 drawn on a2-6-charvram - click to jump there · /RDB · <- 1/8 (also 6H.1, 6K.14) A1 1 /RDB ↗ drawn on a2-6-charvram - click to jump there · $CHWGATE · <- 4H pin 9 B1 2 $CHWGATE ↗ LHBL · <- 5/8 (horizontal blanking) A3 9 LHBL LVBL · <- 5/8 (vertical blanking) B3 10 LVBL CHARA · <- 1F pin 2 A4 12 CHARA CHARB · <- 1F pin 15 B4 13 CHARB drawn on a2-6-charvram - click to jump there · /$CHWE · -> 7F pin 21 (~WE) Y1 3 /$CHWE ↗ /$BLANK · -> 1E pin 12 (D2): resampled before clearing 2E Y3 8 /$BLANK /$CHTRANS · -> 1H pin 6 (A1) + 2F/2H/2J pin 2 (B select) Y4 11 /$CHTRANS GND:7=GND VCC:14=+5V 2F — 74LS153: Source mux (153) for index bits $MIX5/MIX6. Per group: C0=SCR, C1=OBJ, C2=C3=CHAR; A select=/$OBJTRANS (pin 14), B select=/$CHTRANS (pin 2); both strobes GND. Priority char > sprite > scroll. — verified 2026-07-25 2F ✓ 74LS153 GND · strobe tied GND ~1G 1 GND /$CHTRANS · <- 3F pin 11 (NAND CHARA,CHARB): high = char pixel opaque B 2 /$CHTRANS CHARE · <- 1F (C2=C3 so char wins on either A) 1C3 3 CHARE CHARE · <- 1F 1C2 4 CHARE OBJE · sprite (B board) 1C1 5 OBJE SCRE · scroll (C board, CN-1/CN-2) 1C0 6 SCRE SCRF · scroll (C board, CN-1/CN-2) 2C0 10 SCRF OBJF · sprite (B board) 2C1 11 OBJF CHARF · <- 1F 2C2 12 CHARF CHARF · <- 1F 2C3 13 CHARF /$OBJTRANS · <- 3J pin 8 (same net as 1H A0): high = sprite pixel opaque A 14 /$OBJTRANS GND · strobe tied GND ~2G 15 GND $MIX5 · -> 2E 1Y 7 $MIX5 $MIX6 · -> 2E 2Y 9 $MIX6 GND:8=GND VCC:16=+5V 2H — 74LS153: Source mux (153) for index bits $MIX3/MIX4. Per group: C0=SCR, C1=OBJ, C2=C3=CHAR; A select=/$OBJTRANS (pin 14), B select=/$CHTRANS (pin 2); both strobes GND. Priority char > sprite > scroll. — verified 2026-07-25 2H ✓ 74LS153 GND · strobe tied GND ~1G 1 GND /$CHTRANS · <- 3F pin 11 (NAND CHARA,CHARB): high = char pixel opaque B 2 /$CHTRANS CHARC · <- 1F (C2=C3 so char wins on either A) 1C3 3 CHARC CHARC · <- 1F 1C2 4 CHARC OBJC · sprite (B board) 1C1 5 OBJC SCRC · scroll (C board, CN-1/CN-2) 1C0 6 SCRC SCRD · scroll (C board, CN-1/CN-2) 2C0 10 SCRD OBJD · sprite (B board) 2C1 11 OBJD CHARD · <- 1F 2C2 12 CHARD CHARD · <- 1F 2C3 13 CHARD /$OBJTRANS · <- 3J pin 8 (same net as 1H A0): high = sprite pixel opaque A 14 /$OBJTRANS GND · strobe tied GND ~2G 15 GND $MIX3 · -> 2E 1Y 7 $MIX3 $MIX4 · -> 2E 2Y 9 $MIX4 GND:8=GND VCC:16=+5V 2J — 74LS153: Source mux (153) for index bits $MIX1/MIX2. Per group: C0=SCR, C1=OBJ, C2=C3=CHAR; A select=/$OBJTRANS (pin 14), B select=/$CHTRANS (pin 2); both strobes GND. Priority char > sprite > scroll. — verified 2026-07-25 2J ✓ 74LS153 GND · strobe tied GND ~1G 1 GND /$CHTRANS · <- 3F pin 11 (NAND CHARA,CHARB): high = char pixel opaque B 2 /$CHTRANS CHARA · <- 1F (C2=C3 so char wins on either A) 1C3 3 CHARA CHARA · <- 1F 1C2 4 CHARA OBJA · sprite (B board) 1C1 5 OBJA SCRA · scroll (C board, CN-1/CN-2) 1C0 6 SCRA SCRB · scroll (C board, CN-1/CN-2) 2C0 10 SCRB OBJB · sprite (B board) 2C1 11 OBJB CHARB · <- 1F 2C2 12 CHARB CHARB · <- 1F 2C3 13 CHARB /$OBJTRANS · <- 3J pin 8 (same net as 1H A0): high = sprite pixel opaque A 14 /$OBJTRANS GND · strobe tied GND ~2G 15 GND $MIX1 · -> 2E 1Y 7 $MIX1 $MIX2 · -> 2E 2Y 9 $MIX2 GND:8=GND VCC:16=+5V 1H — TBP24S10: Palette-bank PROM (TBP24S10, vtb4). 3-bit address: A0=/$OBJTRANS (3J.8), A1=/$CHTRANS (3F.11), A2=SCRG (CN-1 B12 from C board); A3-A7 + both ~CE tied GND. Outputs D1->2E pin 3 ($BANK1), D0->2E pin 18 ($BANK0); D2/D3 unused. — verified 2026-07-25 1H ✓ TBP24S10 GND · A3-A7 tied GND (only A0-A2 used: 8-entry lookup) A6 1 GND GND · A3-A7 tied GND (only A0-A2 used: 8-entry lookup) A5 2 GND GND · A3-A7 tied GND (only A0-A2 used: 8-entry lookup) A4 3 GND GND · A3-A7 tied GND (only A0-A2 used: 8-entry lookup) A3 4 GND /$OBJTRANS · <- 3J pin 8 (NAND OBJA-D): high = sprite pixel opaque A0 5 /$OBJTRANS /$CHTRANS · <- 3F pin 11 (NAND CHARA,CHARB): high = char pixel opaque A1 6 /$CHTRANS SCRG · <- CN-1 B12 from C board (c1-2-scrollvram 4B pin 12): scroll top colour bit A2 7 SCRG GND · ~CE tied GND - PROM always enabled ~CE1 13 GND GND · ~CE tied GND - PROM always enabled ~CE2 14 GND GND · A3-A7 tied GND (only A0-A2 used: 8-entry lookup) A7 15 GND $BANK1 · -> 2E pin 3 (D0) D1 11 $BANK1 $BANK0 · -> 2E pin 18 (D7) D0 12 $BANK0 GND:8=GND VCC:16=+5V 2E — 74LS273: Pixel-index pipeline latch (273) clocked /$CH6M, ~CL=/$BLANKS (forces index 0 = black when blanked). In: $BANK1(1H.11), $MIX1-6 (2F/2H/2J), $BANK0(1H.12). Out $PIX0-$PIX7 -> A0-A7 of all three colour PROMs 1D/2D/3D. — verified 2026-07-25 2E ✓ 74LS273 /$BLANKS · <- 1E pin 6: clears index to 0 (black) during blanking ~CL 1 /$BLANKS $BANK1 D1 3 $BANK1 $MIX5 · <- 2F pin 7 (1Y) D2 4 $MIX5 $MIX3 · <- 2H pin 7 (1Y) D3 7 $MIX3 $MIX1 · <- 2J pin 7 (1Y) D4 8 $MIX1 CH6M · pixel clock CLK 11 CH6M $MIX2 · <- 2J pin 9 (2Y) D5 13 $MIX2 $MIX4 · <- 2H pin 9 (2Y) D6 14 $MIX4 $MIX6 · <- 2F pin 9 (2Y) D7 17 $MIX6 $BANK0 D8 18 $BANK0 $PIX7 · -> 1D/2D/3D pin 15 (A7) Q1 2 $PIX7 $PIX4 · -> 1D/2D/3D pin 3 (A4) Q2 5 $PIX4 $PIX2 · -> 1D/2D/3D pin 7 (A2) Q3 6 $PIX2 $PIX0 · -> 1D/2D/3D pin 5 (A0) Q4 9 $PIX0 $PIX1 · -> 1D/2D/3D pin 6 (A1) Q5 12 $PIX1 $PIX3 · -> 1D/2D/3D pin 4 (A3) Q6 15 $PIX3 $PIX5 · -> 1D/2D/3D pin 2 (A5) Q7 16 $PIX5 $PIX6 · -> 1D/2D/3D pin 1 (A6) Q8 19 $PIX6 GND:10=GND VCC:20=+5V 1E — 74LS74: Blanking resync (74, two stages on /$CH6M from 3E): /$BLANK (3F.8) -> D2(12), Q2(9) -> D1(2), ~Q1(6) = /$BLANKS -> 2E ~CL. All presets/clears (1,4,10,13) +5. — verified 2026-07-25 1E ✓ 74LS74 +5V ~CL1 1 +5V $BLANKS1 · <- 1E pin 9 D1 2 $BLANKS1 /$CH6M · <- 3E pin 12 CLK1 3 /$CH6M +5V ~PR1 4 +5V +5V ~PR2 10 +5V /$CH6M · <- 3E pin 12 CLK2 11 /$CH6M /$BLANK · <- 3F pin 8 D2 12 /$BLANK +5V ~CL2 13 +5V /$BLANKS · -> 2E pin 1 (~CL): clears pixel index to black ~Q1 6 /$BLANKS $BLANKS1 · -> 1E pin 2 (D1): stage 1 of 2 Q2 9 $BLANKS1 GND:7=GND VCC:14=+5V 3E — 74LS04: One inverter of the 04 on this sheet: /$CH6M (13) -> /$CH6M (12), the clock for both 1E blanking-sync FFs. — verified 2026-07-25 3E ✓ 74LS04 drawn on a2-7-chargen - click to jump there · CHHFLIPa · <- 7D pin 10 (sheet 6) raw char h-flip A 1 CHHFLIPa ↗ drawn on a2-6-charvram - click to jump there · /D0CS · char window D000-D7FF select from 2/8 | renamed 2026-07-27: same net as io 3B pin 6 /$D0CS (D000-D7FF) - was a letter-O vs zero split A3 5 /D0CS ↗ CH6M · <- 7/8 pixel clock A 13 CH6M drawn on a2-7-chargen - click to jump there · /$CHHFLIP · -> 4C pin 4 Y 2 /$CHHFLIP ↗ drawn on a2-6-charvram - click to jump there · $D0CS · -> 6F pin 10 + 4H pin 13 | renamed 2026-07-27: same net as io 3B pin 6 /$D0CS (D000-D7FF) - was a letter-O vs zero split Y3 6 $D0CS ↗ /$CH6M · output is not lettered on the sheet; /$CH6M is our name (Robert confirmed the gate itself, 2026-07-27) Y 12 /$CH6M GND:7=GND VCC:14=+5V 1D — TBP24S10: RED palette PROM (TBP24S10, vtb1). A0-A7 = $PIX0-7 from 2E; both ~CE tied GND. D0-D3 -> R43-R46 resistor ladder -> edge 5. — verified 2026-07-25 1D ✓ TBP24S10 $PIX6 · <- 2E (shared index bus) A6 1 $PIX6 $PIX5 · <- 2E (shared index bus) A5 2 $PIX5 $PIX4 · <- 2E (shared index bus) A4 3 $PIX4 $PIX3 · <- 2E (shared index bus) A3 4 $PIX3 $PIX0 · <- 2E (shared index bus) A0 5 $PIX0 $PIX1 · <- 2E (shared index bus) A1 6 $PIX1 $PIX2 · <- 2E (shared index bus) A2 7 $PIX2 GND · ~CE tied GND - always enabled ~CE1 13 GND GND · ~CE tied GND - always enabled ~CE2 14 GND $PIX7 · <- 2E (shared index bus) A7 15 $PIX7 $RED3 · -> R43-R46 ladder -> edge 5 D3 9 $RED3 $RED2 · -> R43-R46 ladder -> edge 5 D2 10 $RED2 $RED1 · -> R43-R46 ladder -> edge 5 D1 11 $RED1 $RED0 · -> R43-R46 ladder -> edge 5 D0 12 $RED0 GND:8=GND VCC:16=+5V 2D — TBP24S10: GRN palette PROM (TBP24S10, vtb2). A0-A7 = $PIX0-7 from 2E; both ~CE tied GND. D0-D3 -> R47-R50 resistor ladder -> edge E. — verified 2026-07-25 2D ✓ TBP24S10 $PIX6 · <- 2E (shared index bus) A6 1 $PIX6 $PIX5 · <- 2E (shared index bus) A5 2 $PIX5 $PIX4 · <- 2E (shared index bus) A4 3 $PIX4 $PIX3 · <- 2E (shared index bus) A3 4 $PIX3 $PIX0 · <- 2E (shared index bus) A0 5 $PIX0 $PIX1 · <- 2E (shared index bus) A1 6 $PIX1 $PIX2 · <- 2E (shared index bus) A2 7 $PIX2 GND · ~CE tied GND - always enabled ~CE1 13 GND GND · ~CE tied GND - always enabled ~CE2 14 GND $PIX7 · <- 2E (shared index bus) A7 15 $PIX7 $GRN3 · -> R47-R50 ladder -> edge E D3 9 $GRN3 $GRN2 · -> R47-R50 ladder -> edge E D2 10 $GRN2 $GRN1 · -> R47-R50 ladder -> edge E D1 11 $GRN1 $GRN0 · -> R47-R50 ladder -> edge E D0 12 $GRN0 GND:8=GND VCC:16=+5V 3D — TBP24S10: BLU palette PROM (TBP24S10, vtb3). A0-A7 = $PIX0-7 from 2E; both ~CE tied GND. D0-D3 -> R51-R54 resistor ladder -> edge 6. — verified 2026-07-25 3D ✓ TBP24S10 $PIX6 · <- 2E (shared index bus) A6 1 $PIX6 $PIX5 · <- 2E (shared index bus) A5 2 $PIX5 $PIX4 · <- 2E (shared index bus) A4 3 $PIX4 $PIX3 · <- 2E (shared index bus) A3 4 $PIX3 $PIX0 · <- 2E (shared index bus) A0 5 $PIX0 $PIX1 · <- 2E (shared index bus) A1 6 $PIX1 $PIX2 · <- 2E (shared index bus) A2 7 $PIX2 GND · ~CE tied GND - always enabled ~CE1 13 GND GND · ~CE tied GND - always enabled ~CE2 14 GND $PIX7 · <- 2E (shared index bus) A7 15 $PIX7 $BLU3 · -> R51-R54 ladder -> edge 6 D3 9 $BLU3 $BLU2 · -> R51-R54 ladder -> edge 6 D2 10 $BLU2 $BLU1 · -> R51-R54 ladder -> edge 6 D1 11 $BLU1 $BLU0 · -> R51-R54 ladder -> edge 6 D0 12 $BLU0 GND:8=GND VCC:16=+5V
· Original scan — manual p30 · zoom
original schematic scan
1F
3J
3F
2F
2H
2J
1H
2E
1E
3E
1D
2D
3D