85605-A-2 Sheet 1/1 — CUSTOM CHIP

manual p31 · 3 ICs · 3 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Neither board has this chip - both use a PAL16L8 instead:The dirty board - PAL16L8 riserdaughter board in the 10M socket (MAME commandob, set 1)The clean board - PAL16L8 on the PCBno riser; set 2 hardware, set 3 ROMs
10M — CUSTOM DIP48: Capcom 85605 opcode decryptor (custom DIP48) between Z80 and program ROMs. CPU-side bus D0-D7 primes on pins 45,42,40,38,35,33,31,29; memory-side on 46,44,41,39,37,34,32,30. A0-A15 on 3,4,5,7,8,9,10,11,12,14,15,17,19,20,18,16. RNW=/WR(2), SYNC=/M1 via 11J(47), E=$MREQ AND /RFSH via 6N(28), NRST=/RESET AND /IN5 via 6N(27). NAHE/NALE/MNS/VDD +5; NMEMD(23)+VSS GND. — verified 2026-07-25 10M ✓ CUSTOM DIP48 /WR RNW 2 /WR A0 AB0 3 A0 A1 AB1 4 A1 A2 AB2 5 A2 A3 AB3 7 A3 A4 AB4 8 A4 A5 AB5 9 A5 A6 AB6 10 A6 A7 AB7 11 A7 A8 AB8 12 A8 A9 AB9 14 A9 A10 AB10 15 A10 A15 AB15 16 A15 A11 AB11 17 A11 A14 AB14 18 A14 A12 AB12 19 A12 A13 AB13 20 A13 +5V NAHE 21 +5V +5V NALE 22 +5V GND · tied GND with the VSS pins NMEMD 23 GND +5V MNS 26 +5V $NRST10M · <- 6N pin 8 (NRST = /RESET AND /IN5) NRST 27 $NRST10M $E10M · <- 6N pin 11 (E = $MREQ AND /RFSH) E 28 $E10M D7' DB7 29 D7' D7 DX7 30 D7 D6' DB6 31 D6' D6 DX6 32 D6 D5' DB5 33 D5' D5 DX5 34 D5 D4' DB4 35 D4' D4 DX4 37 D4 D3' DB3 38 D3' D3 DX3 39 D3 D2' DB2 40 D2' D2 DX2 41 D2 D1' DB1 42 D1' D1 DX1 44 D1 D0' DB0 45 D0' D0 DX0 46 D0 $SYNC10M · <- 11J pin 6 (/M1 inverted; C33 220pF on the /M1 node) SYNC 47 $SYNC10M VSS:1=GND VSS:6=GND VSS:13=GND VSS:24=GND VDD:25=+5V VSS:36=GND VSS:43=GND VDD:48=+5V 6N — 74LS08: Two AND units of the 08: NRST = /ACL2 AND /IN5 (pins 10,9 -> 8) resets the 10M decryptor on power-on clear or a C005 port read; E = $MREQ AND /RFSH (pins 12,13 -> 11). — verified 2026-07-25 6N ✓ 74LS08 drawn on a2-1-cpu - click to jump there · BLCNTEN · walkthrough 2026-07-21: CN-1 B23 from the B board - opens the RAM for sprite DMA during blanking A2 4 BLCNTEN ↗ drawn on a2-1-cpu - click to jump there · /CSEF B2 5 /CSEF ↗ /IN5 · <- a2-2-io 3A pin 10 (/IN5, C005 read strobe) - closes that sheet-2 open end B3 9 /IN5 /ACL1 · <- a2-1-cpu 11J pin 4. Continuity confirmed 2026-07-25 (and NOT /RES: 11J pin 8 read open) A3 10 /ACL1 $MREQ · <- 11J pin 2 ($MREQ) A4 12 $MREQ /RFSH · <- /RFSH B4 13 /RFSH drawn on a2-1-cpu - click to jump there · /$RAMCS Y2 6 /$RAMCS ↗ $NRST10M · -> 10M pin 27 (NRST) Y3 8 $NRST10M $E10M · -> 10M pin 28 (E) Y4 11 $E10M GND:7=GND VCC:14=+5V 11J — 74LS14: Schmitt inverters: /M1 -> SYNC (opcode-fetch strobe, C33 220 pF hangs on the /M1 node) and /$MREQ -> $MREQ for the E gate — verified 2026-07-25 11J ✓ 74LS14 /MREQ · <- /$MREQ A1 1 /MREQ drawn on a2-1-cpu - click to jump there · $RESNODE A2 3 $RESNODE ↗ /M1 · <- /M1 (C33 220pF to GND on this node) A3 5 /M1 drawn on a2-1-cpu - click to jump there · $RESNODE A4 9 $RESNODE ↗ drawn on a2-1-cpu - click to jump there · $PSTOUT A5 11 $PSTOUT ↗ drawn on a2-1-cpu - click to jump there · BLCNTEN · walkthrough 2026-07-21: /$BLCNTEN in - inverter completes DIR = /RDB OR /$BLCNTEN A6 13 BLCNTEN ↗ $MREQ · -> 6N pin 12 Y1 2 $MREQ drawn on a2-1-cpu - click to jump there · /ACL1 · driver. Drawn /ACL2 locally, leaves as /ACL1 on CN-1 B19 to 2/8 + 3/8. Single node - continuity confirmed 2026-07-25 Y2 4 /ACL1 ↗ $SYNC10M · -> 10M pin 47 (SYNC) Y3 6 $SYNC10M drawn on a2-1-cpu - click to jump there · /$RES Y4 8 /$RES ↗ drawn on a2-1-cpu - click to jump there · $RESNODE Y5 10 $RESNODE ↗ drawn on a2-1-cpu - click to jump there · /$BLCNTEN Y6 12 /$BLCNTEN ↗ GND:7=GND VCC:14=+5V
· Original scan — manual p31 · zoom
original schematic scan
10M
6N
11J