85605-B-1 Sheet 1/6 — 96 OBJECTS DATA RAM

manual p32 · 19 ICs · 19 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Interboard connectors (the band cables between the boards) — circled letter+number labels on the drawing are connector row + pin
1D — 74LS245: Address/strobe buffer high (245), DIR=GND (B->A), ~G=BLCNTEN. AB8<-OB8; AB9-AB12 set by RA1 10K pull-ups + J1 jumper block (selects the sprite-table base address); /RDB driven LOW (B7=GND) and /WRB held HIGH (B6=+5) during the DMA window - the B board only reads. A8/B8 (pins 9,11) unused. — verified 2026-07-25 1D ✓ 74LS245 GND · DIR=GND: B->A during DMA DIR 1 GND AB8 A1 2 AB8 AB9 A2 3 AB9 AB10 A3 4 AB10 AB11 A4 5 AB11 AB12 A5 6 AB12 /WRB · driven HIGH during DMA (B6=+5): DMA never writes A6 7 /WRB /RDB · driven LOW during DMA (B7=GND): asserts the read strobe A7 8 /RDB GND · asserts /RDB B7 12 GND +5V · holds /WRB deasserted B6 13 +5V $J1AB12 · +5 via RA1 10K pull-up, J1 jumper option -> sets AB12 B5 14 $J1AB12 $J1AB11 · +5 via RA1 10K pull-up, J1 jumper option -> sets AB11 B4 15 $J1AB11 $J1AB10 · +5 via RA1 10K pull-up, J1 jumper option -> sets AB10 B3 16 $J1AB10 $J1AB9 · +5 via RA1 10K pull-up, J1 jumper option -> sets AB9 B2 17 $J1AB9 OB8 · <- 2/6 counter B1 18 OB8 BLCNTEN · <- CN-1 B23 ~G 19 BLCNTEN GND:10=GND VCC:20=+5V 1C — 74LS245: Address buffer low (245): OB0-OB7 (2/6 counters) -> AB0-AB7 on CN-1 during DMA. DIR=GND (B->A), ~G=BLCNTEN. — verified 2026-07-25 1C ✓ 74LS245 GND · DIR=GND: B->A (B board drives the A-board address bus during DMA) DIR 1 GND AB0 · A side -> CN-1 (A-board address bus) A1 2 AB0 AB1 · A side -> CN-1 (A-board address bus) A2 3 AB1 AB2 · A side -> CN-1 (A-board address bus) A3 4 AB2 AB3 · A side -> CN-1 (A-board address bus) A4 5 AB3 AB4 · A side -> CN-1 (A-board address bus) A5 6 AB4 AB5 · A side -> CN-1 (A-board address bus) A6 7 AB5 AB6 · A side -> CN-1 (A-board address bus) A7 8 AB6 AB7 · A side -> CN-1 (A-board address bus) A8 9 AB7 OB7 · B side <- 2/6 object counters B8 11 OB7 OB6 · B side <- 2/6 object counters B7 12 OB6 OB5 · B side <- 2/6 object counters B6 13 OB5 OB4 · B side <- 2/6 object counters B5 14 OB4 OB3 · B side <- 2/6 object counters B4 15 OB3 OB2 · B side <- 2/6 object counters B3 16 OB2 OB1 · B side <- 2/6 object counters B2 17 OB1 OB0 · B side <- 2/6 object counters B1 18 OB0 BLCNTEN · ~G <- BLCNTEN (CN-1 B23): buffer enabled for the DMA window ~G 19 BLCNTEN GND:10=GND VCC:20=+5V 1E — 74LS245: Data buffer (245): DB0-DB7 from the A board -> DE0-DE7 object data bus during DMA. DIR=+5 (A->B), ~G=BLCNTEN. — verified 2026-07-25 1E ✓ 74LS245 +5V · DIR=+5: A->B (A-board data bus into the object data bus) DIR 1 +5V DB0 · A side <- CN-1 A1-A8 (A-board data bus) A1 2 DB0 DB1 · A side <- CN-1 A1-A8 (A-board data bus) A2 3 DB1 DB2 · A side <- CN-1 A1-A8 (A-board data bus) A3 4 DB2 DB3 · A side <- CN-1 A1-A8 (A-board data bus) A4 5 DB3 DB4 · A side <- CN-1 A1-A8 (A-board data bus) A5 6 DB4 DB5 · A side <- CN-1 A1-A8 (A-board data bus) A6 7 DB5 DB6 · A side <- CN-1 A1-A8 (A-board data bus) A7 8 DB6 DB7 · A side <- CN-1 A1-A8 (A-board data bus) A8 9 DB7 DE7 · B side -> DE bus: 1A/2A RAM + 2D/3D staging B8 11 DE7 DE6 · B side -> DE bus: 1A/2A RAM + 2D/3D staging B7 12 DE6 DE5 · B side -> DE bus: 1A/2A RAM + 2D/3D staging B6 13 DE5 DE4 · B side -> DE bus: 1A/2A RAM + 2D/3D staging B5 14 DE4 DE3 · B side -> DE bus: 1A/2A RAM + 2D/3D staging B4 15 DE3 DE2 · B side -> DE bus: 1A/2A RAM + 2D/3D staging B3 16 DE2 DE1 · B side -> DE bus: 1A/2A RAM + 2D/3D staging B2 17 DE1 DE0 · B side -> DE bus: 1A/2A RAM + 2D/3D staging B1 18 DE0 BLCNTEN · ~G <- BLCNTEN (CN-1 B23): enabled for the DMA window ~G 19 BLCNTEN GND:10=GND VCC:20=+5V 1A — 2114: Object RAM high nibble (2114, 1Kx4). Address OB0-OB8 shared with the twin; A9(15) and ~CS(8) tied GND; ~WE(10) from 6B pin 8. Data DE4-DE7 on pins 14,13,12,11. — verified 2026-07-25 1A ✓ 2114 OB6 · <- 2/6 object counters (OB bus) A6 1 OB6 OB5 · <- 2/6 object counters (OB bus) A5 2 OB5 OB4 · <- 2/6 object counters (OB bus) A4 3 OB4 OB3 · <- 2/6 object counters (OB bus) A3 4 OB3 OB0 · <- 2/6 object counters (OB bus) A0 5 OB0 OB1 · <- 2/6 object counters (OB bus) A1 6 OB1 OB2 · <- 2/6 object counters (OB bus) A2 7 OB2 GND · ~CS tied GND - always selected ~CS 8 GND /$OBWE · ~WE <- 6B pin 8 (/$OBWE) ~WE 10 /$OBWE DE7 · object data bus (DE) IO4 11 DE7 DE6 · object data bus (DE) IO3 12 DE6 DE5 · object data bus (DE) IO2 13 DE5 DE4 · object data bus (DE) IO1 14 DE4 GND · A9 tied GND - only OB0-OB8 used (96 sprites x 4 bytes) A9 15 GND OB8 · <- 2/6 object counters (OB bus) A8 16 OB8 OB7 · <- 2/6 object counters (OB bus) A7 17 OB7 GND:9=GND VCC:18=+5V 2A — 2114: Object RAM low nibble (2114, 1Kx4). Address OB0-OB8 shared with the twin; A9(15) and ~CS(8) tied GND; ~WE(10) from 6B pin 8. Data DE0-DE3 on pins 14,13,12,11. — verified 2026-07-25 2A ✓ 2114 OB6 · <- 2/6 object counters (OB bus) A6 1 OB6 OB5 · <- 2/6 object counters (OB bus) A5 2 OB5 OB4 · <- 2/6 object counters (OB bus) A4 3 OB4 OB3 · <- 2/6 object counters (OB bus) A3 4 OB3 OB0 · <- 2/6 object counters (OB bus) A0 5 OB0 OB1 · <- 2/6 object counters (OB bus) A1 6 OB1 OB2 · <- 2/6 object counters (OB bus) A2 7 OB2 GND · ~CS tied GND - always selected ~CS 8 GND /$OBWE · ~WE <- 6B pin 8 (/$OBWE) ~WE 10 /$OBWE DE3 · object data bus (DE) IO4 11 DE3 DE2 · object data bus (DE) IO3 12 DE2 DE1 · object data bus (DE) IO2 13 DE1 DE0 · object data bus (DE) IO1 14 DE0 GND · A9 tied GND - only OB0-OB8 used (96 sprites x 4 bytes) A9 15 GND OB8 · <- 2/6 object counters (OB bus) A8 16 OB8 OB7 · <- 2/6 object counters (OB bus) A7 17 OB7 GND:9=GND VCC:18=+5V 6B — 74LS32: Quad OR (32), all four gates on this sheet: g1 OBASEL+$STAGEGATE(5B.4)->/$OBAEN to 2D pin 19; g2 OVER96+/$ROB->6A pin 5 (DMA request self-release); g3 PHIBB+BLCNTEN(5B.10)->/$OBWE to 1A/2A pin 10 (writes only during the DMA window); g4 OBBSEL+$STAGEGATE->/$OBBEN to 3D pin 19. — verified 2026-07-25 6B ✓ 74LS32 OBASEL · <- 2/6 B1 1 OBASEL $STAGEGATE · <- 5B pin 4 A1 2 $STAGEGATE /OVER96 · <- 2/6 8B pin 11. Slash joined 2026-07-27 A2 4 /OVER96 /ROB · <- 6C pin 5 B2 5 /ROB BPHIBB · <- 2/6 9A pin 12 (B-board phi-BB, = H1 inverted). Renamed from PHIBB 2026-07-26: the A-board PHIBB (a2-3-sound 8E) is a different signal A3 9 BPHIBB BLCNTEN · <- 5B pin 10 (BLCNTEN): so /$OBWE = PHIBB AND BLCNTEN - object RAM writes only inside the DMA window B3 10 BLCNTEN OBBSEL · <- 2/6 B4 12 OBBSEL $STAGEGATE · <- 5B pin 4 A4 13 $STAGEGATE /$OBAEN · -> 2D pin 19 (~EN) Y1 3 /$OBAEN $DMAEND · -> 6A pin 5 Y2 6 $DMAEND /$OBWE · -> 1A pin 10 (~WE) + 2A pin 10 (shared RAM pair) Y3 8 /$OBWE /$OBBEN · -> 3D pin 19 (~EN) Y4 11 /$OBBEN GND:7=GND VCC:14=+5V 6A — 74LS08: One AND gate of the 08 drawn here: /ACL1 (CN-1 B19, drawn ACL2) AND 6B pin 6 -> 6C pin 4 (~PR1). Presets the request FF on power-on clear or DMA end. Other gates of the package not drawn on this sheet. — verified 2026-07-25 6A ✓ 74LS08 drawn on b1-4-objrom - click to jump there · V1a · <- 6F pin 5 A1 1 V1a ↗ drawn on b1-4-objrom - click to jump there · FLIP · <- 1/6 B1 2 FLIP ↗ /ACL1 · <- CN-1 B19 (drawn ACL2 on this sheet; same wire as A-board /ACL1) A2 4 /ACL1 $DMAEND · <- 6B pin 6 B2 5 $DMAEND drawn on b1-2-objcontroller - click to jump there · $SEQ9C1 · <- 9C pin 3 A3 9 $SEQ9C1 ↗ drawn on b1-2-objcontroller - click to jump there · $LINEOR · <- 8C pin 6 B3 10 $LINEOR ↗ drawn on b1-4-objrom - click to jump there · /$V1a · <- 9K pin 12 A4 12 /$V1a ↗ drawn on b1-4-objrom - click to jump there · FLIP · <- 1/6 (same vertical that feeds pin 2) B4 13 FLIP ↗ drawn on b1-4-objrom - click to jump there · OBFLIP2 · -> 6/6 Y1 3 OBFLIP2 ↗ $DMAPR · -> 6C pin 4 (~PR1): releases the bus request Y2 6 $DMAPR drawn on b1-2-objcontroller - click to jump there · $OBJLD · -> 7B pin 9, 7A pin 9, 10B pin 5 Y3 8 $OBJLD ↗ drawn on b1-4-objrom - click to jump there · OBFLIP1 · -> 5/6 Y4 11 OBFLIP1 ↗ GND:7=GND VCC:14=+5V 6C — 74LS74: DMA handshake FFs (74). Unit1 = bus request: D1=GND, CLK1=/OKOUT (CN-1 B20), ~PR1 from 6A pin 6; Q1=/$ROB out on CN-1 B22 + 6B pin 5; ~Q1 ($ROB) -> unit2 ~PR2. Unit2 = grant latch: D2=/AKB (CN-1 B21, also to 2/6), CLK2=PHIBB, ~PR2 from unit1; ~Q2 = BLEN -> 2/6 + 5B pin 11; Q2 (pin 9) NC. Both ~CL +5. — verified 2026-07-25 6C ✓ 74LS74 +5V ~CL1 1 +5V GND · tied GND D1 2 GND /OKOUT · <- CN-1 B20 (A board C806 write) CLK1 3 /OKOUT $DMAPR · <- 6A pin 6 ~PR1 4 $DMAPR $ROB · <- 6C pin 6 ~PR2 10 $ROB BPHIBB · <- 2/6 9A pin 12 (B-board phi-BB, = H1 inverted). Renamed from PHIBB 2026-07-26: the A-board PHIBB (a2-3-sound 8E) is a different signal CLK2 11 BPHIBB /AKB · <- CN-1 B21, also out to 2/6 D2 12 /AKB +5V ~CL2 13 +5V /ROB · -> CN-1 B22 (bus request to A board) + 6B pin 5 Q1 5 /ROB $ROB · ~Q1 complement -> 6C pin 10 (~PR2) ~Q1 6 $ROB BLEN · -> 2/6 and 5B pin 11 ~Q2 8 BLEN GND:7=GND VCC:14=+5V 5B — 74LS04: Hex inverter (04): four V-flip complements /$V16F/V32F/V64F/V128F -> /$V16F,/$V32F,/$V64F,/$V128F into the 2B adder (subtract trick); OVER96 (3) -> $STAGEGATE (4) to 6B pins 2+13; BLEN (11, from 6C pin 8) -> BLCNTEN (10), which leaves on CN-1 B23 to the A board and also gates 6B pin 10. — verified 2026-07-25 5B ✓ 74LS04 V32F A1 1 V32F /OVER96 · <- 2/6 8B pin 11. Slash joined 2026-07-27 A2 3 /OVER96 V16F A3 5 V16F V128F A4 9 V128F BLEN · <- 6C pin 8 A5 11 BLEN V64F A6 13 V64F /$V32F · -> 2B adder Y1 2 /$V32F $STAGEGATE · -> 6B pins 2 and 13 Y2 4 $STAGEGATE /$V16F · -> 2B adder Y3 6 /$V16F /$V128F · -> 2B adder Y4 8 /$V128F BLCNTEN · inverts BLEN -> BLCNTEN: out on CN-1 B23 to the A board, and to 6B pin 10. Drawing marks it /BLCNTEN here Y5 10 BLCNTEN /$V64F · -> 2B adder Y6 12 /$V64F GND:7=GND VCC:14=+5V 5A — 74LS86: V flip XORs (86): V16/V32/V64/V128 XOR FLIPB (4B pin 10) -> flipped copies. FLIP on pins 2,5,10,13. — verified 2026-07-25 5A ✓ 74LS86 V16 · <- CN-2 (raw V counter bit) A1 1 V16 $FLIPb · <- 4B pin 10 (buffered FLIP; drawing note "2,5,10,13 x2") B1 2 $FLIPb V32 · <- CN-2 (raw V counter bit) A2 4 V32 $FLIPb · <- 4B pin 10 (buffered FLIP; drawing note "2,5,10,13 x2") B2 5 $FLIPb V64 · <- CN-2 (raw V counter bit) A3 9 V64 $FLIPb · <- 4B pin 10 (buffered FLIP; drawing note "2,5,10,13 x2") B3 10 $FLIPb V128 · <- CN-2 (raw V counter bit) A4 12 V128 $FLIPb · <- 4B pin 10 (buffered FLIP; drawing note "2,5,10,13 x2") B4 13 $FLIPb V16F · flipped V bit -> 5B//4B inverters + adders, and to 3/6 Y1 3 V16F V32F · flipped V bit -> 5B//4B inverters + adders, and to 3/6 Y2 6 V32F V64F · flipped V bit -> 5B//4B inverters + adders, and to 3/6 Y3 8 V64F V128F · flipped V bit -> 5B//4B inverters + adders, and to 3/6 Y4 11 V128F GND:7=GND VCC:14=+5V 4A — 74LS86: V flip XORs (86): V1/V2/V4/V8 XOR FLIPB (4B pin 10) -> flipped copies. FLIP on pins 2,5,10,13. — verified 2026-07-25 4A ✓ 74LS86 V1 · <- CN-2 (raw V counter bit) A1 1 V1 $FLIPb · <- 4B pin 10 (buffered FLIP; drawing note "2,5,10,13 x2") B1 2 $FLIPb V2 · <- CN-2 (raw V counter bit) A2 4 V2 $FLIPb · <- 4B pin 10 (buffered FLIP; drawing note "2,5,10,13 x2") B2 5 $FLIPb V4 · <- CN-2 (raw V counter bit) A3 9 V4 $FLIPb · <- 4B pin 10 (buffered FLIP; drawing note "2,5,10,13 x2") B3 10 $FLIPb V8 · <- CN-2 (raw V counter bit) A4 12 V8 $FLIPb · <- 4B pin 10 (buffered FLIP; drawing note "2,5,10,13 x2") B4 13 $FLIPb V1F · flipped V bit -> 5B//4B inverters + adders, and to 3/6 Y1 3 V1F V2F · flipped V bit -> 5B//4B inverters + adders, and to 3/6 Y2 6 V2F V4F · flipped V bit -> 5B//4B inverters + adders, and to 3/6 Y3 8 V4F V8F · flipped V bit -> 5B//4B inverters + adders, and to 3/6 Y4 11 V8F GND:7=GND VCC:14=+5V 4B — 74LS04: Inverter pack distributing FLIP on the B board. FLIP (CN-2 D2) in on pin 3; pin 4 = /FLIP (lettered on the drawing) to 2B/3B and back into pin 11; pin 11 -> pin 10 = $FLIPb, FLIP restored and re-buffered, to 4A/5A pins 2,5,10,13 - that output is bare on the drawing, so only its name is ours. — verified 2026-07-25 4B ✓ 74LS04 V2F · <- 4A pin 6 A1 1 V2F FLIP · <- CN-2 D2 A2 3 FLIP V1F · <- 4A pin 3 A3 5 V1F V8F · <- 4A pin 11 A4 9 V8F /FLIP · <- 4B pin 4 A5 11 /FLIP V4F · <- 4A pin 8 A6 13 V4F /$V2F · -> 3B adder B input Y1 2 /$V2F /FLIP · -> 4B pin 11, 2B pins 3,5,12,14 (A inputs), 3B pins 12,14 Y2 4 /FLIP /$V1F · -> 3B adder B input Y3 6 /$V1F /$V8F · -> 3B adder B input Y4 8 /$V8F $FLIPb · no text on this wire (Robert, 2026-07-27). Our name for FLIP re-buffered - a DIFFERENT net from /FLIP on pin 4, which IS lettered; never merge the two. Y5 10 $FLIPb /$V4F · -> 3B adder B input Y6 12 /$V4F GND:7=GND VCC:14=+5V 2B — 74LS283: Offset adder high nibble (283): B=/$V16F../$V128F (5B complements) + A=/FLIP on all four. Sums $VO16-$VO128 -> 2C B inputs (pins 6,2,15,11). C0 from 3B pin 9; C4 unused. — verified 2026-07-25 2B ✓ 74LS283 /$V32F · <- 5B pin 2 B2 2 /$V32F /FLIP · <- 4B pin 4 A2 3 /FLIP /FLIP · <- 4B pin 4 A1 5 /FLIP /$V16F · <- 5B pin 6 B1 6 /$V16F $YOFC1 · <- 3B pin 9 C0 7 $YOFC1 /$V128F · <- 5B pin 8 B4 11 /$V128F /FLIP · <- 4B pin 4 A4 12 /FLIP /FLIP · <- 4B pin 4 A3 14 /FLIP /$V64F · <- 5B pin 12 B3 15 /$V64F $VO32 · -> 2C pin 2 S2 1 $VO32 $VO16 · -> 2C pin 6 S1 4 $VO16 $VO128 · -> 2C pin 11 S4 10 $VO128 $VO64 · -> 2C pin 15 S3 13 $VO64 GND:8=GND VCC:16=+5V 3B — 74LS283: Offset adder low nibble (283): B=/$V1F../$V8F (4B complements) + A=(A4,A3=/FLIP; A2=+5, A1=GND). Sums $VO1-$VO8 -> 3C B inputs (pins 6,2,15,11). C0=GND, C4 -> 2B pin 7. — verified 2026-07-25 3B ✓ 74LS283 /$V2F · <- 4B pin 2 B2 2 /$V2F +5V A2 3 +5V GND A1 5 GND /$V1F · <- 4B pin 6 B1 6 /$V1F GND · no carry in C0 7 GND /$V8F · <- 4B pin 8 B4 11 /$V8F /FLIP · <- 4B pin 4 A4 12 /FLIP /FLIP · <- 4B pin 4 A3 14 /FLIP /$V4F · <- 4B pin 12 B3 15 /$V4F $VO2 · -> 3C pin 2 S2 1 $VO2 $VO1 · -> 3C pin 6 S1 4 $VO1 $YOFC1 · -> 2B pin 7 C4 9 $YOFC1 $VO8 · -> 3C pin 11 S4 10 $VO8 $VO4 · -> 3C pin 15 S3 13 $VO4 GND:8=GND VCC:16=+5V 2C — 74LS283: Y-match adder high nibble (283): sprite Y high (DE4-DE7) + offset V high (2B sums), carry in from 3C. All four sums -> 2E; C4 unused. YM* names are ours - unlabelled on the drawing. — verified 2026-07-25 2C ✓ 74LS283 $VO32 · <- 2B sum (offset V high) B2 2 $VO32 DE5 · <- object RAM high nibble (1A) via DE bus A2 3 DE5 DE4 · <- object RAM high nibble (1A) via DE bus A1 5 DE4 $VO16 · <- 2B sum (offset V high) B1 6 $VO16 $YMC1 · <- 3C pin 9 C0 7 $YMC1 $VO128 · <- 2B sum (offset V high) B4 11 $VO128 DE7 · <- object RAM high nibble (1A) via DE bus A4 12 DE7 DE6 · <- object RAM high nibble (1A) via DE bus A3 14 DE6 $VO64 · <- 2B sum (offset V high) B3 15 $VO64 $YM32 · -> 2E match NAND S2 1 $YM32 $YM16 · -> 2E match NAND S1 4 $YM16 $YM128 · -> 2E match NAND S4 10 $YM128 $YM64 · -> 2E match NAND S3 13 $YM64 GND:8=GND VCC:16=+5V 3C — 74LS283: Y-match adder low nibble (283): sprite Y low (DE0-DE3) + offset V low (3B sums). Sums unused; only C4 (pin 9) -> 2C pin 7. Net names VO*/DE* are ours - wires unlabelled on the drawing. — verified 2026-07-25 3C ✓ 74LS283 $VO2 · <- 3B sum (offset V low) B2 2 $VO2 DE1 · <- object RAM low nibble (2A) via DE bus A2 3 DE1 DE0 · <- object RAM low nibble (2A) via DE bus A1 5 DE0 $VO1 · <- 3B sum (offset V low) B1 6 $VO1 GND C0 7 GND $VO8 · <- 3B sum (offset V low) B4 11 $VO8 DE3 · <- object RAM low nibble (2A) via DE bus A4 12 DE3 DE2 · <- object RAM low nibble (2A) via DE bus A3 14 DE2 $VO4 · <- 3B sum (offset V low) B3 15 $VO4 $YMC1 · -> 2C pin 7 (carry into high nibble) C4 9 $YMC1 GND:8=GND VCC:16=+5V 2E — 74LS20: Y-match NAND (20): all four high sum bits from 2C high = scanline inside the sprite 16-row band -> /MATCH (pin 8) to 2/6. Other gate of the package not drawn here. — verified 2026-07-25 2E ✓ 74LS20 drawn on b1-3-objdatacontrol - click to jump there · LVb5 · <- 5E sum (stage-2 high nibble) | Capcom writes this with a Greek letter; we spell it lowercase C 1 LVb5 ↗ drawn on b1-3-objdatacontrol - click to jump there · LVb7 · <- 5E sum (stage-2 high nibble) | Capcom writes this with a Greek letter; we spell it lowercase A 2 LVb7 ↗ drawn on b1-3-objdatacontrol - click to jump there · LVb4 · <- 5E sum (stage-2 high nibble) | Capcom writes this with a Greek letter; we spell it lowercase D 4 LVb4 ↗ drawn on b1-3-objdatacontrol - click to jump there · LVb6 · <- 5E sum (stage-2 high nibble) | Capcom writes this with a Greek letter; we spell it lowercase B 5 LVb6 ↗ $YM32 · <- 2C sum bit C 9 $YM32 $YM16 · <- 2C sum bit D 10 $YM16 $YM64 · <- 2C sum bit B 12 $YM64 $YM128 · <- 2C sum bit A 13 $YM128 drawn on b1-3-objdatacontrol - click to jump there · /VINZONE · -> 4/6: line-in-sprite qualifier Y 6 /VINZONE ↗ /MATCH · -> /MATCH to 2/6 Y 8 /MATCH GND:7=GND VCC:14=+5V 2D — 74LS245: Staging buffer (245): DE0-DE7 -> DEA0-DEA7 to sheet 3/6. DIR=+5 (A->B), ~G=/$OBAEN from 6B pin 3. — verified 2026-07-25 2D ✓ 74LS245 +5V · DIR=+5: A->B DIR 1 +5V DE7 · <- DE object data bus A1 2 DE7 DE6 · <- DE object data bus A2 3 DE6 DE5 · <- DE object data bus A3 4 DE5 DE4 · <- DE object data bus A4 5 DE4 DE3 · <- DE object data bus A5 6 DE3 DE2 · <- DE object data bus A6 7 DE2 DE1 · <- DE object data bus A7 8 DE1 DE0 · <- DE object data bus A8 9 DE0 /$OBAEN · ~G <- 6B pin 3 (/$OBAEN) ~G 19 /$OBAEN DEA0 · -> 3/6 (sprite entry half) B8 11 DEA0 DEA1 · -> 3/6 (sprite entry half) B7 12 DEA1 DEA2 · -> 3/6 (sprite entry half) B6 13 DEA2 DEA3 · -> 3/6 (sprite entry half) B5 14 DEA3 DEA4 · -> 3/6 (sprite entry half) B4 15 DEA4 DEA5 · -> 3/6 (sprite entry half) B3 16 DEA5 DEA6 · -> 3/6 (sprite entry half) B2 17 DEA6 DEA7 · -> 3/6 (sprite entry half) B1 18 DEA7 GND:10=GND VCC:20=+5V 3D — 74LS245: Staging buffer (245): DE0-DE7 -> DEB0-DEB7 to sheet 3/6. DIR=+5 (A->B), ~G=/$OBBEN from 6B pin 11. — verified 2026-07-25 3D ✓ 74LS245 +5V · DIR=+5: A->B DIR 1 +5V DE7 · <- DE object data bus A1 2 DE7 DE6 · <- DE object data bus A2 3 DE6 DE5 · <- DE object data bus A3 4 DE5 DE4 · <- DE object data bus A4 5 DE4 DE3 · <- DE object data bus A5 6 DE3 DE2 · <- DE object data bus A6 7 DE2 DE1 · <- DE object data bus A7 8 DE1 DE0 · <- DE object data bus A8 9 DE0 /$OBBEN · ~G <- 6B pin 11 (/$OBBEN) ~G 19 /$OBBEN DEB0 · -> 3/6 (sprite entry half) B8 11 DEB0 DEB1 · -> 3/6 (sprite entry half) B7 12 DEB1 DEB2 · -> 3/6 (sprite entry half) B6 13 DEB2 DEB3 · -> 3/6 (sprite entry half) B5 14 DEB3 DEB4 · -> 3/6 (sprite entry half) B4 15 DEB4 DEB5 · -> 3/6 (sprite entry half) B3 16 DEB5 DEB6 · -> 3/6 (sprite entry half) B2 17 DEB6 DEB7 · -> 3/6 (sprite entry half) B1 18 DEB7 GND:10=GND VCC:20=+5V
· Original scan — manual p32 · zoom
original schematic scan
1D
1C
1E
1A
2A
6B
6A
6C
5B
5A
4A
4B
2B
3B
2C
3C
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3D