85605-B-1 Sheet 2/6 — 24/96 OBJECT CONTROLLER

manual p33 · 15 ICs · 15 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
7C — 74LS161: Byte counter (161) clocked by /$BPHIBB. Load inputs are DRIVEN not strapped: A=GND, B from 8A pin 6, C+D from 8A pin 12 - so it preloads 12 or 2 depending on the scan-state term. ~CL=/OVER24 (9D.11), ~LD from 10B pin 6, P/T=+5. Outputs OB0(14)/OB1(13); QD(11) -> 9A pin 1 + 10C pin 10; QC(12) not drawn. CA(15) -> 8C pin 13 + 7D P/T. — verified 2026-07-26 7C ✓ 74LS161 /OVER24 · <- 9D pin 11 (also to 10C pin 13) | overbar confirmed on the sheet (Robert, 2026-07-27) ~CL 1 /OVER24 BPHIBB · <- 9A pin 12 (B-board phi-BB, = H1 inverted) CLK 2 BPHIBB GND A 3 GND /$SCANST · <- 8A pin 6 B 4 /$SCANST $SCANST · <- 8A pin 12 C 5 $SCANST $SCANST · <- 8A pin 12 (same net as C) D 6 $SCANST +5V P 7 +5V /$BYTELD · <- 10B pin 6 ~LO 9 /$BYTELD +5V T 10 +5V $OB1Y · -> 9A pin 1 + 10C pin 10 QD 11 $OB1Y OB1 · -> 1/6 and 3/6 QB 13 OB1 OB0 · -> 1/6 and 3/6 QA 14 OB0 $BYTECA · -> 8C pin 13, and 7D pins 7+10 (P/T) CA 15 $BYTECA GND:8=GND VCC:16=+5V 7B — 74LS161: Object index counter low (161): OB2-OB5 on pins 14/13/12/11. Clocked /$BPHIBB; ~CL tied +5 (never cleared); ~LD from 6A pin 8 (shared with 7A); P/T from 8C pin 11 so it advances once per 4-byte entry; A-D grounded. CA(15)=$OBCARRY -> 7A P/T + 8A pin 9. — verified 2026-07-26 7B ✓ 74LS161 +5V · never cleared ~CL 1 +5V BPHIBB · <- 9A pin 12 (B-board phi-BB, = H1 inverted) CLK 2 BPHIBB GND A 3 GND GND B 4 GND GND C 5 GND GND D 6 GND $OBADV · <- 8C pin 11 P 7 $OBADV $OBJLD · <- 6A pin 8 ~LO 9 $OBJLD $OBADV · <- 8C pin 11 T 10 $OBADV OB5 · -> OB bus (1/6, 3/6) QD 11 OB5 OB4 · -> OB bus (1/6, 3/6) QC 12 OB4 OB3 · -> OB bus (1/6, 3/6) QB 13 OB3 OB2 · -> OB bus (1/6, 3/6) QA 14 OB2 $OBCARRY · -> 7A pins 7 and 10 (P/T), and 8A pin 9 CA 15 $OBCARRY GND:8=GND VCC:16=+5V 7A — 74LS161: Object index counter high (161): OB6(14)/OB7(13)/OB8(12). Clocked /$BPHIBB; ~CL tied +5; ~LD from 6A pin 8 (shared with 7B); P/T from 7B pin 15 ($OBCARRY) so it advances on the low counter rollover; A-D grounded (loads 0). QD(11) and CA(15) unused - the index only needs 7 bits for 0-95. — verified 2026-07-26 7A ✓ 74LS161 +5V · never cleared, like 7B ~CL 1 +5V BPHIBB · <- 9A pin 12 (B-board phi-BB, = H1 inverted) CLK 2 BPHIBB GND · load value 0 A 3 GND GND · load value 0 B 4 GND GND · load value 0 C 5 GND GND · load value 0 D 6 GND $OBCARRY · <- 7B pin 15 P 7 $OBCARRY $OBJLD · <- 6A pin 8 ~LO 9 $OBJLD $OBCARRY · <- 7B pin 15 T 10 $OBCARRY OB8 · -> 8A pin 10, 8B pin 13 QC 12 OB8 OB7 · -> 8B pin 12/13 (/OVER96 gate) QB 13 OB7 OB6 · -> 8A pin 11 QA 14 OB6 GND:8=GND VCC:16=+5V 7D — 74LS161: Line-store slot counter low (161): OBA0-OBA3. Clocked /$BPHIBB, ~CL=+5, ~LD from 10B pin 8 (shared with 8D), P/T from 7C pin 15 ($BYTECA). Load value 8 (D tied +5, A-C GND). CA -> 8D P/T. — verified 2026-07-26 7D ✓ 74LS161 +5V · never cleared ~CL 1 +5V BPHIBB · <- 9A pin 12 (B-board phi-BB, = H1 inverted) CLK 2 BPHIBB GND A 3 GND GND B 4 GND GND C 5 GND +5V · load value = 8 (D only) D 6 +5V $BYTECA · <- 7C pin 15 P 7 $BYTECA /$SLOTLD · <- 10B pin 8 (shared with 8D pin 9) ~LO 9 /$SLOTLD $BYTECA · <- 7C pin 15 T 10 $BYTECA OBA3 · -> 3/6 (line-store slot address) QD 11 OBA3 OBA2 · -> 3/6 (line-store slot address) QC 12 OBA2 OBA1 · -> 3/6 (line-store slot address) QB 13 OBA1 OBA0 · -> 3/6 (line-store slot address) QA 14 OBA0 $SLOTCA · -> 8D pins 7 and 10 CA 15 $SLOTCA GND:8=GND VCC:16=+5V 8D — 74LS161: Slot counter high (161): OBA4 on pin 14. Loads 0; P/T from 7D carry. QB (pin 13) is bit 5 of the pair - it sets when the count passes 31, i.e. exactly 24 slots after the preloaded 8 - and drives 9D pin 12 to make /OVER24. QC/QD/CA unused. — verified 2026-07-26 8D ✓ 74LS161 +5V · never cleared ~CL 1 +5V BPHIBB · <- 9A pin 12 (B-board phi-BB, = H1 inverted) CLK 2 BPHIBB GND · load value = 0 A 3 GND GND · load value = 0 B 4 GND GND · load value = 0 C 5 GND GND · load value = 0 D 6 GND $SLOTCA · <- 7D pin 15 P 7 $SLOTCA /$SLOTLD · <- 10B pin 8 (shared with 7D pin 9) ~LO 9 /$SLOTLD $SLOTCA · <- 7D pin 15 T 10 $SLOTCA $SLOT32 · bit 5 of the pair: sets at count 32 = 24 slots used -> 9D pin 12 QB 13 $SLOT32 OBA4 · -> 3/6 (slot address MSB) QA 14 OBA4 GND:8=GND VCC:16=+5V 9A — 74LS04: Hex inverter (04), all six gates used. 1->2: $OB1Y -> /$OB1Y (10B.1). 3->4: H256 -> 9B clock. 5->6: /$BYTEDONE -> /$BYTEDONE (8C.10). 9->8: 8C pin 3 -> 10B pin 4. 11->10: /$BPHIBB -> /$BPHIBB (10C.9). 13->12: H1 -> /$BPHIBB, the object-scan clock for all five counters + out to sheet 1/6. — verified 2026-07-26 9A ✓ 74LS04 $OB1Y · <- 7C pin 11 A1 1 $OB1Y H256 · <- 3/6 A2 3 H256 $BYTEDONE · <- 10B pin 3 (also 10B pin 12, 8C pin 1) A3 5 $BYTEDONE $SEQ8C1 · <- 8C pin 3 A4 9 $SEQ8C1 BPHIBB · <- 9A pin 12 A5 11 BPHIBB H1 · <- 3/6 A6 13 H1 /$OB1Y · -> 10B pin 1 Y1 2 /$OB1Y $H256B · -> 9B CLK (pin 3) Y2 4 $H256B /$BYTEDONE · -> 8C pin 10 Y3 6 /$BYTEDONE $SEQ9A4 · -> 10B pin 4 Y4 8 $SEQ9A4 /$BPHIBB · -> 10C pin 9 Y5 10 /$BPHIBB BPHIBB · B-board phi-BB: 5 counter clocks + 9A.11 + out to sheet 1/6 Y6 12 BPHIBB GND:7=GND VCC:14=+5V 10B — 74LS08: Quad AND (08). g1: /$OB1Y (9A.2) AND OB1 -> /$BYTEDONE. g4: /$BYTEDONE AND /MATCH -> $STORE, to 8C pin 12. g2: 9A pin 8 AND $OBJLD -> /$BYTELD to 7C pin 9. g3: /24-96TM (9B.6) AND /HINIT -> /$SLOTLD to 7D+8D pin 9. — verified 2026-07-26 10B ✓ 74LS08 /$OB1Y · <- 9A pin 2 A1 1 /$OB1Y OB1 · <- 7C pin 13 B1 2 OB1 $SEQ9A4 · <- 9A pin 8 A2 4 $SEQ9A4 $OBJLD · <- 6A pin 8 B2 5 $OBJLD /24_96TM · <- 9B pin 6 A3 9 /24_96TM /HINITB · <- CN-2 C18 (same net as 8B pin 5) B3 10 /HINITB $BYTEDONE · <- 10B pin 3 A4 12 $BYTEDONE /MATCH · <- 1/6 (2E pin 8) B4 13 /MATCH $BYTEDONE · -> 10B pin 12 Y1 3 $BYTEDONE /$BYTELD · -> 7C pin 9 Y2 6 /$BYTELD /$SLOTLD · -> 7D pin 9 and 8D pin 9 Y3 8 /$SLOTLD $STORE · -> 8C pin 12 Y4 11 $STORE GND:7=GND VCC:14=+5V 8C — 74LS32: Quad OR (32), all four gates. g1: /$BYTEDONE + $BYTECA -> 9A pin 9. g2: /HINIT + 24-96TM -> 6A pin 10. g3: /MATCH + /$BYTEDONE -> 8A pin 13. g4: $STORE + $BYTECA -> $OBADV, advancing the object index (7B P/T). — verified 2026-07-26 8C ✓ 74LS32 $BYTEDONE · <- 10B pin 3 A1 1 $BYTEDONE $BYTECA · <- 7C pin 15 B1 2 $BYTECA /HINITB · <- CN-2 C18 A2 4 /HINITB 24_96TM · <- 9B pin 5 B2 5 24_96TM /MATCH · <- 1/6 (2E pin 8) A3 9 /MATCH /$BYTEDONE · <- 9A pin 6 B3 10 /$BYTEDONE $STORE · <- 10B pin 11 A4 12 $STORE $BYTECA · <- 7C pin 15 B4 13 $BYTECA $SEQ8C1 · -> 9A pin 9 Y1 3 $SEQ8C1 $LINEOR · -> 6A pin 10 Y2 6 $LINEOR $SEQ8C · -> 8A pin 13 Y3 8 $SEQ8C $OBADV · -> 7B pins 7 and 10 (object index advance) Y4 11 $OBADV GND:7=GND VCC:14=+5V 8A — 74LS10: Triple 3-input NAND (10). g1: NAND(8B.6, /AKB, 8C.8) -> pin 12 = scan-state term, to 8A pin 3 + 7C load inputs C/D. g2: pins 4,5 tied +5 so it inverts pin 3 -> pin 6 to 7C load input B. g3: NAND($OBCARRY, OB8, OB6) -> pin 8 to 8B pin 9. — verified 2026-07-26 8A ✓ 74LS10 $SEQ8B · <- 8B pin 6 (measured; NOT the +5 rail) A1 1 $SEQ8B /AKB · <- CN-1 B21 via 1/6 B1 2 /AKB $SCANST · <- 8A pin 12 A2 3 $SCANST +5V B2 4 +5V +5V C2 5 +5V $OBCARRY · <- 7B pin 15; same net feeds 7A pins 7 and 10 A3 9 $OBCARRY OB8 · <- 7A pin 12 (also 8B pin 13) B3 10 OB8 OB6 · <- 7A pin 14 C3 11 OB6 $SEQ8C · <- 8C pin 8 C1 13 $SEQ8C /$SCANST · gate 2 = inverter (B,C tied +5) -> 7C pin 4 Y2 6 /$SCANST $SEQ8A3 · -> 8B pin 9 Y3 8 $SEQ8A3 $SCANST · -> 8A pin 3 and 7C pins 5,6 Y1 12 $SCANST GND:7=GND VCC:14=+5V 8B — 74LS00: Quad NAND (00), three gates used. g4: NAND(OB7, OB8) = /OVER96 -> 1/6, ending the 96-object scan at index 96 (64+32). g3: NAND(8A pin 8, /OVER96) -> pin 8. g2: NAND(that, /HINIT) -> 8A pin 1. Gate 1 not drawn on this sheet. — verified 2026-07-26 8B ✓ 74LS00 $SEQ8B3 · <- 8B pin 8 (gate 3 output) A2 4 $SEQ8B3 /HINITB · <- CN-2 C18 (A-board 2N pin 2); also to 10B pin 10 B2 5 /HINITB $SEQ8A3 · <- 8A pin 8 A3 9 $SEQ8A3 /OVER96 · <- 8B pin 11 (gate 4 output); overbar confirmed on the sheet (Robert, 2026-07-27) B3 10 /OVER96 OB7 · <- 7A pin 13 A4 12 OB7 OB8 · <- 7A pin 12 (Robert read 2026-07-26) B4 13 OB8 $SEQ8B · -> 8A pin 1 Y2 6 $SEQ8B $SEQ8B3 · -> 8B pin 4 Y3 8 $SEQ8B3 /OVER96 · -> 1/6 (6B pin 4 + 5B pin 3): ends the 96-object scan Y4 11 /OVER96 GND:7=GND VCC:14=+5V 6A — 74LS08: One AND gate of the 08 drawn on this sheet: 9C pin 3 AND $LINEOR (8C pin 6) -> $OBJLD (pin 8), which reloads both object counters (7A/7B pin 9) and gates 10B pin 5. Other gates of the package not drawn here. — verified 2026-07-26 6A ✓ 74LS08 drawn on b1-4-objrom - click to jump there · V1a · <- 6F pin 5 A1 1 V1a ↗ drawn on b1-4-objrom - click to jump there · FLIP · <- 1/6 B1 2 FLIP ↗ drawn on b1-1-objram - click to jump there · /ACL1 · <- CN-1 B19 (drawn ACL2 on this sheet; same wire as A-board /ACL1) A2 4 /ACL1 ↗ drawn on b1-1-objram - click to jump there · $DMAEND · <- 6B pin 6 B2 5 $DMAEND ↗ $SEQ9C1 · <- 9C pin 3 A3 9 $SEQ9C1 $LINEOR · <- 8C pin 6 B3 10 $LINEOR drawn on b1-4-objrom - click to jump there · /$V1a · <- 9K pin 12 A4 12 /$V1a ↗ drawn on b1-4-objrom - click to jump there · FLIP · <- 1/6 (same vertical that feeds pin 2) B4 13 FLIP ↗ drawn on b1-4-objrom - click to jump there · OBFLIP2 · -> 6/6 Y1 3 OBFLIP2 ↗ drawn on b1-1-objram - click to jump there · $DMAPR · -> 6C pin 4 (~PR1): releases the bus request Y2 6 $DMAPR ↗ $OBJLD · -> 7B pin 9, 7A pin 9, 10B pin 5 Y3 8 $OBJLD drawn on b1-4-objrom - click to jump there · OBFLIP1 · -> 5/6 Y4 11 OBFLIP1 ↗ GND:7=GND VCC:14=+5V 9D — 74LS86: Two XOR units used as inverters (other input tied +5). g4: $SLOT32 (8D pin 13) -> /OVER24 (pin 11) to 7C ~CL and 10C pin 13. g3: /$LV1 from 4/6 -> /$LV1 (pin 8) to 9C pin 9. Gates 1 and 2 not drawn on this sheet. — verified 2026-07-26 9D ✓ 74LS86 LV1 · <- 4/6 A3 9 LV1 +5V · XOR with 1 = inverter B3 10 +5V $SLOT32 · <- 8D pin 13 A4 12 $SLOT32 +5V · XOR with 1 = inverter B4 13 +5V /$LV1 · -> 9C pin 9 Y3 8 /$LV1 /OVER24 · -> 7C pin 1 (~CL) and 10C pin 13 | overbar confirmed on the sheet (Robert, 2026-07-27) Y4 11 /OVER24 GND:7=GND VCC:14=+5V 9B — 74LS74: Line-phase FF (74), first half only. BLTIMING (from 4/6) sampled on $H256B (9A pin 4) -> Q = 24/96TM, the signal that splits each scanline into the 96-object search and the 24-sprite playback; ~Q -> 10B pin 9. Both ~CL and ~PR tied +5. Second FF (pins 8-13) not drawn - parked. The second flip-flop of the package is unused: not drawn on any B-board sheet and confirmed with no tracks on the board. — verified 2026-07-26 9B ✓ 74LS74 +5V ~CL1 1 +5V BLTIMING · <- 4/6 D1 2 BLTIMING $H256B CLK1 3 $H256B +5V ~PR1 4 +5V 24_96TM · line phase -> 3/6 and 9C Q 5 24_96TM /24_96TM · -> 10B pin 9 ~Q 6 /24_96TM GND:7=GND VCC:14=+5V 9C — 74LS32: Quad OR (32), three gates drawn. g1: BLEN + /24-96TM -> 6A pin 9 (part of the counter reload). g2: /$LV1 + 24-96TM -> OBBSEL. g3: /$LV1 + 24-96TM -> OBASEL. The two SEL outputs are complementary in /$LV1 and both held high during the 96-object search, so /$LV1 alternates the staging buffers (2D/3D on sheet 1/6) during playback. — verified 2026-07-26 9C ✓ 74LS32 BLEN · <- 1/6 A1 1 BLEN /24_96TM · <- 9B pin 6 (also 10B pin 9, 10C pin 12) B1 2 /24_96TM LV1 · <- 4/6 A2 4 LV1 24_96TM · <- 9B pin 5 B2 5 24_96TM /$LV1 · <- 9D pin 8 A3 9 /$LV1 24_96TM · <- 9B pin 5 B3 10 24_96TM drawn on b1-4-objrom - click to jump there · OBHFLIPa · <- 3/6 2F pin 12 A4 12 OBHFLIPa ↗ drawn on b1-4-objrom - click to jump there · 4-3H · <- CN-2 C4 B4 13 4-3H ↗ $SEQ9C1 · -> 6A pin 9 Y1 3 $SEQ9C1 OBBSEL · -> 3/6 and 1/6 (6B pin 12) Y2 6 OBBSEL OBASEL · -> 1/6 (6B pin 1) and 3/6 Y3 8 OBASEL drawn on b1-4-objrom - click to jump there · $OBS0 · -> all four shifters pin 9 Y4 11 $OBS0 ↗ GND:7=GND VCC:14=+5V 10C — 74LS20: Staging write strobe (20, 4-input NAND): /$BPHIBB (9A.10) + $OB1Y (7C.11) + /24-96TM (9B.6) + /OVER24 (9D.11) -> /OBJABWR to 3/6. So a sprite is written to the line store only on the right byte, in the playback phase, before the 24-slot limit is hit, timed by the inverted clock. First gate not drawn on this sheet. — verified 2026-07-26 10C ✓ 74LS20 /$BPHIBB · <- 9A pin 10 B 9 /$BPHIBB $OB1Y · <- 7C pin 11 B 10 $OB1Y /24_96TM · <- 9B pin 6 A 12 /24_96TM /OVER24 · <- 9D pin 11 | overbar confirmed on the sheet (Robert, 2026-07-27) C 13 /OVER24 /OBJABWR · -> 3/6: writes the matched sprite into the line store Y 8 /OBJABWR GND:7=GND VCC:14=+5V
· Original scan — manual p33 · zoom
original schematic scan
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