85605-B-1 Sheet 3/6 — OBJECT DATA CONTROL

manual p34 · 28 ICs · 28 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Interboard connectors (the band cables between the boards) — circled letter+number labels on the drawing are connector row + pin
1H — 74LS157: Bank-A address mux low (157): SEL=/OBASEL picks store (OB0,OB1,OBA0,OBA1) vs playback (H2,H4,H16,H32); Y -> 2114 A0-A3. ST grounded. — verified 2026-07-26 1H ✓ 74LS157 OBASEL · <- 2/6 (9C pin 8): store vs playback SEL 1 OBASEL OB0 · store addr A1 2 OB0 H2 · playback addr B1 3 H2 OB1 · store addr A2 5 OB1 H4 · playback addr B2 6 H4 H16 · playback addr B3 10 H16 OBA0 · store addr A3 11 OBA0 H32 · playback addr B4 13 H32 OBA1 · store addr A4 14 OBA1 GND · strobe tied low ~ST 15 GND $SA0 · -> 4H/3H pin 5 Y1 4 $SA0 $SA1 · -> 4H/3H pin 6 Y2 7 $SA1 $SA2 · -> 4H/3H pin 7 Y3 9 $SA2 $SA3 · -> 4H/3H pin 4 Y4 12 $SA3 GND:8=GND VCC:16=+5V 2H — 74LS157: Bank-A address mux high (157): store (OBA2,OBA3,OBA4,/OBJABWR) vs playback (H64,H128,H256,+5); Y -> 2114 A4-A6 and /WE. The fourth unit muxes the WRITE STROBE, so writes can only happen in the store phase. — verified 2026-07-26 2H ✓ 74LS157 OBASEL · <- 2/6 (9C pin 8): store vs playback SEL 1 OBASEL OBA2 · store addr A1 2 OBA2 H64 · playback addr B1 3 H64 OBA3 · store addr A2 5 OBA3 H128 · playback addr B2 6 H128 H256 · playback addr B3 10 H256 OBA4 · store addr A3 11 OBA4 +5V · no write during playback B4 13 +5V /OBJABWR · store write strobe <- 2/6 10C pin 8 A4 14 /OBJABWR GND · strobe tied low ~ST 15 GND $SA4 · -> 4H/3H pin 3 Y1 4 $SA4 $SA5 · -> 4H/3H pin 2 Y2 7 $SA5 $SA6 · -> 4H/3H pin 1 Y3 9 $SA6 /$SAWE · -> 4H/3H pin 10 Y4 12 /$SAWE GND:8=GND VCC:16=+5V 4H — 2114: Bank-A line store, high nibble DEA4-DEA7 (2114). Address A0-A6 from the 1H/2H muxes; A7-A9 tied +5 (top 128 bytes of the 1K); ~CS grounded; ~WE from 2H pin 12. — verified 2026-07-26 4H ✓ 2114 $SA6 · <- 1H/2H mux A6 1 $SA6 $SA5 · <- 1H/2H mux A5 2 $SA5 $SA4 · <- 1H/2H mux A4 3 $SA4 $SA3 · <- 1H/2H mux A3 4 $SA3 $SA0 · <- 1H/2H mux A0 5 $SA0 $SA1 · <- 1H/2H mux A1 6 $SA1 $SA2 · <- 1H/2H mux A2 7 $SA2 GND · always selected ~CS 8 GND /$SAWE · <- 2H pin 12 ~WE 10 /$SAWE DEA7 · DEA bus (RA2 4.7k pull-ups) IO4 11 DEA7 DEA6 · DEA bus (RA2 4.7k pull-ups) IO3 12 DEA6 DEA5 · DEA bus (RA2 4.7k pull-ups) IO2 13 DEA5 DEA4 · DEA bus (RA2 4.7k pull-ups) IO1 14 DEA4 +5V · top of the 1K space A9 15 +5V +5V · top of the 1K space A8 16 +5V +5V · top of the 1K space A7 17 +5V GND:9=GND VCC:18=+5V 3H — 2114: Bank-A line store, low nibble DEA0-DEA3 (2114). Same addressing and control as 4H. — verified 2026-07-26 3H ✓ 2114 $SA6 · <- 1H/2H mux A6 1 $SA6 $SA5 · <- 1H/2H mux A5 2 $SA5 $SA4 · <- 1H/2H mux A4 3 $SA4 $SA3 · <- 1H/2H mux A3 4 $SA3 $SA0 · <- 1H/2H mux A0 5 $SA0 $SA1 · <- 1H/2H mux A1 6 $SA1 $SA2 · <- 1H/2H mux A2 7 $SA2 GND · always selected ~CS 8 GND /$SAWE · <- 2H pin 12 ~WE 10 /$SAWE DEA3 · DEA bus (RA2 4.7k pull-ups) IO4 11 DEA3 DEA2 · DEA bus (RA2 4.7k pull-ups) IO3 12 DEA2 DEA1 · DEA bus (RA2 4.7k pull-ups) IO2 13 DEA1 DEA0 · DEA bus (RA2 4.7k pull-ups) IO1 14 DEA0 +5V · top of the 1K space A9 15 +5V +5V · top of the 1K space A8 16 +5V +5V · top of the 1K space A7 17 +5V GND:9=GND VCC:18=+5V 1J — 74LS157: Bank-B address mux low (157): SEL=/OBBSEL picks store (OB0,OB1,OBA0,OBA1) vs playback (H2,H4,H16,H32); Y -> 2114 A0-A3. Mirror of 1H. — verified 2026-07-26 1J ✓ 74LS157 OBBSEL · <- 2/6 (9C pin 6): store vs playback SEL 1 OBBSEL OB0 · store side A1 2 OB0 H2 · playback side B1 3 H2 OB1 · store side A2 5 OB1 H4 · playback side B2 6 H4 H16 · playback side B3 10 H16 OBA0 · store side A3 11 OBA0 H32 · playback side B4 13 H32 OBA1 · store side A4 14 OBA1 GND · strobe tied low ~ST 15 GND $SB0 · -> 3J/4J pin 5 Y1 4 $SB0 $SB1 · -> 3J/4J pin 6 Y2 7 $SB1 $SB2 · -> 3J/4J pin 7 Y3 9 $SB2 $SB3 · -> 3J/4J pin 4 Y4 12 $SB3 GND:8=GND VCC:16=+5V 2J — 74LS157: Bank-B address mux high (157): store (OBA2,OBA3,OBA4,/OBJABWR) vs playback (H64,H128,H256,+5); Y -> A4-A6 and /WE. Mirror of 2H. — verified 2026-07-26 2J ✓ 74LS157 OBBSEL · <- 2/6 (9C pin 6): store vs playback SEL 1 OBBSEL OBA2 · store side A1 2 OBA2 H64 · playback side B1 3 H64 OBA3 · store side A2 5 OBA3 H128 · playback side B2 6 H128 H256 · playback side B3 10 H256 OBA4 · store side A3 11 OBA4 +5V · playback side B4 13 +5V /OBJABWR · store side A4 14 /OBJABWR GND · strobe tied low ~ST 15 GND $SB4 · -> 3J/4J pin 3 Y1 4 $SB4 $SB5 · -> 3J/4J pin 2 Y2 7 $SB5 $SB6 · -> 3J/4J pin 1 Y3 9 $SB6 /$SBWE · -> 3J/4J pin 10 Y4 12 /$SBWE GND:8=GND VCC:16=+5V 3J — 2114: Bank-B line store, high nibble DEB4-DEB7 (2114). A0-A6 from 1J/2J; A7-A9 +5; ~CS GND; ~WE from 2J pin 12. — verified 2026-07-26 3J ✓ 2114 $SB6 · <- 1J/2J mux A6 1 $SB6 $SB5 · <- 1J/2J mux A5 2 $SB5 $SB4 · <- 1J/2J mux A4 3 $SB4 $SB3 · <- 1J/2J mux A3 4 $SB3 $SB0 · <- 1J/2J mux A0 5 $SB0 $SB1 · <- 1J/2J mux A1 6 $SB1 $SB2 · <- 1J/2J mux A2 7 $SB2 GND · always selected ~CS 8 GND /$SBWE · <- 2J pin 12 ~WE 10 /$SBWE DEB7 · DEB bus (RA3 4.7k pull-ups) IO4 11 DEB7 DEB6 · DEB bus (RA3 4.7k pull-ups) IO3 12 DEB6 DEB5 · DEB bus (RA3 4.7k pull-ups) IO2 13 DEB5 DEB4 · DEB bus (RA3 4.7k pull-ups) IO1 14 DEB4 +5V · top of the 1K space A9 15 +5V +5V · top of the 1K space A8 16 +5V +5V · top of the 1K space A7 17 +5V GND:9=GND VCC:18=+5V 4J — 2114: Bank-B line store, low nibble DEB0-DEB3 (2114). Same as 3J. — verified 2026-07-26 4J ✓ 2114 $SB6 · <- 1J/2J mux A6 1 $SB6 $SB5 · <- 1J/2J mux A5 2 $SB5 $SB4 · <- 1J/2J mux A4 3 $SB4 $SB3 · <- 1J/2J mux A3 4 $SB3 $SB0 · <- 1J/2J mux A0 5 $SB0 $SB1 · <- 1J/2J mux A1 6 $SB1 $SB2 · <- 1J/2J mux A2 7 $SB2 GND · always selected ~CS 8 GND /$SBWE · <- 2J pin 12 ~WE 10 /$SBWE DEB3 · DEB bus (RA3 4.7k pull-ups) IO4 11 DEB3 DEB2 · DEB bus (RA3 4.7k pull-ups) IO3 12 DEB2 DEB1 · DEB bus (RA3 4.7k pull-ups) IO2 13 DEB1 DEB0 · DEB bus (RA3 4.7k pull-ups) IO1 14 DEB0 +5V · top of the 1K space A9 15 +5V +5V · top of the 1K space A8 16 +5V +5V · top of the 1K space A7 17 +5V GND:9=GND VCC:18=+5V 5H — 74LS157: Playback mux high nibble (157): DEA4-DEA7 (A side) vs DEB4-DEB7 (B side) -> DF4-DF7. SEL=LV1 from 4/6 selects the bank; ~ST=24/96TM so the DF bus is only driven during playback (outputs forced low in the search phase). — verified 2026-07-26 5H ✓ 74LS157 LV1 · <- 4/6: picks which bank is played back this line SEL 1 LV1 DEA7 A1 2 DEA7 DEB7 B1 3 DEB7 DEA6 A2 5 DEA6 DEB6 B2 6 DEB6 DEB5 B3 10 DEB5 DEA5 A3 11 DEA5 DEB4 B4 13 DEB4 DEA4 A4 14 DEA4 24_96TM · <- 2/6 (9B pin 5): outputs only active in the playback phase ~ST 15 24_96TM DF7 Y1 4 DF7 DF6 Y2 7 DF6 DF5 Y3 9 DF5 DF4 Y4 12 DF4 GND:8=GND VCC:16=+5V 5J — 74LS157: Playback mux low nibble (157): DEA0-DEA3 vs DEB0-DEB3 -> DF0-DF3. SEL=LV1, ~ST=24/96TM, same as 5H. — verified 2026-07-26 5J ✓ 74LS157 LV1 · <- 4/6: picks which bank is played back this line SEL 1 LV1 DEA3 A1 2 DEA3 DEB3 B1 3 DEB3 DEA2 A2 5 DEA2 DEB2 B2 6 DEB2 DEB1 B3 10 DEB1 DEA1 A3 11 DEA1 DEB0 B4 13 DEB0 DEA0 A4 14 DEA0 24_96TM · <- 2/6 (9B pin 5): outputs only active in the playback phase ~ST 15 24_96TM DF3 Y1 4 DF3 DF2 Y2 7 DF2 DF1 Y3 9 DF1 DF0 Y4 12 DF0 GND:8=GND VCC:16=+5V 5F — 74LS373: Sprite Y-byte latch (373): DF0-DF7 -> Va0-Va7 feeding the row adders. Latch enable from 8B pin 3, so the Y byte is captured at its slot in the 4-byte sequence; ~OE grounded so the outputs are always live. — verified 2026-07-26 5F ✓ 74LS373 GND · outputs permanently enabled ~OC 1 GND DF0 D1 3 DF0 DF1 D2 4 DF1 DF2 D3 7 DF2 DF3 D4 8 DF3 $VALATCH · <- 8B pin 3 LE 11 $VALATCH DF4 D5 13 DF4 DF5 D6 14 DF5 DF6 D7 17 DF6 DF7 D8 18 DF7 Va0 · Capcom writes this with a Greek letter; we spell it lowercase Q1 2 Va0 Va1 · Capcom writes this with a Greek letter; we spell it lowercase Q2 5 Va1 Va2 · Capcom writes this with a Greek letter; we spell it lowercase Q3 6 Va2 Va3 · Capcom writes this with a Greek letter; we spell it lowercase Q4 9 Va3 Va4 · Capcom writes this with a Greek letter; we spell it lowercase Q5 12 Va4 Va5 · Capcom writes this with a Greek letter; we spell it lowercase Q6 15 Va5 Va6 · Capcom writes this with a Greek letter; we spell it lowercase Q7 16 Va6 Va7 · Capcom writes this with a Greek letter; we spell it lowercase Q8 19 Va7 GND:10=GND VCC:20=+5V 5C — 74LS175: V-high latch (175) clocked by 4H (CN-2 D4), ~CL=+5. D = V16F/V32F/V64F/V128F (flipped V counter from 1/6). Only the INVERTED outputs are used (/$V16L../$V128L on pins 3,6,11,14) -> 5D adder: feeding /V into an adder is the two-complement subtract that works out the sprite row. — verified 2026-07-26 5C ✓ 74LS175 +5V · never cleared ~CL 1 +5V V16F D1 4 V16F V32F D2 5 V32F 4H · <- CN-2 D4 (a2-5-sync 4N pin 5). Distinct from H4 on C6 CLK 9 4H V64F D3 12 V64F V128F D4 13 V128F /$V16L · -> 5D adder B input ~Q1 3 /$V16L /$V32L · -> 5D adder B input ~Q2 6 /$V32L /$V64L · -> 5D adder B input ~Q3 11 /$V64L /$V128L · -> 5D adder B input ~Q4 14 /$V128L GND:8=GND VCC:16=+5V 4C — 74LS175: V-low latch (175), same clock and clear. D = V1F/V2F/V4F/V8F; inverted outputs /$V1L../$V8L (pins 3,6,11,14) -> 4D adder. Q outputs unused on both latches. — verified 2026-07-26 4C ✓ 74LS175 +5V · never cleared ~CL 1 +5V V1F D1 4 V1F V2F D2 5 V2F 4H · <- CN-2 D4 (a2-5-sync 4N pin 5). Distinct from H4 on C6 CLK 9 4H V4F D3 12 V4F V8F D4 13 V8F /$V1L · -> 4D adder B input ~Q1 3 /$V1L /$V2L · -> 4D adder B input ~Q2 6 /$V2L /$V4L · -> 4D adder B input ~Q3 11 /$V4L /$V8L · -> 4D adder B input ~Q4 14 /$V8L GND:8=GND VCC:16=+5V 4D — 74LS283: Row adder stage 1, low nibble (283). B = /$V1L../$V8L from the 4C latch. A = {A1=+5, A2-A4 = $FLIPC from 1F pin 12}, C0 grounded. With $FLIPC low the constant is 0x01 so the sum is /V+1 = -V, the two-complement negate; with $FLIPC high it becomes 0xFF, shifting the offset for the flipped screen. Carry -> 5D. — verified 2026-07-26 4D ✓ 74LS283 /$V2L B2 2 /$V2L $FLIPC · <- 1F pin 12 A2 3 $FLIPC +5V · the +1 of the two-complement negate A1 5 +5V /$V1L B1 6 /$V1L GND · no carry in C0 7 GND /$V8L B4 11 /$V8L $FLIPC · <- 1F pin 12 A4 12 $FLIPC $FLIPC · <- 1F pin 12 A3 14 $FLIPC /$V4L B3 15 /$V4L $RW2 S2 1 $RW2 $RW1 S1 4 $RW1 $ROWC1 C4 9 $ROWC1 $RW8 S4 10 $RW8 $RW4 S3 13 $RW4 GND:8=GND VCC:16=+5V 5D — 74LS283: Row adder stage 1, high nibble (283). B = /$V16L../$V128L from 5C; all four A inputs = $FLIPC (1F pin 12); C0 from 4D pin 9. Sums $RW16-$RW128 feed stage 2 (5E). — verified 2026-07-26 5D ✓ 74LS283 /$V32L B2 2 /$V32L $FLIPC · <- 1F pin 12 A2 3 $FLIPC $FLIPC · <- 1F pin 12 A1 5 $FLIPC /$V16L B1 6 /$V16L $ROWC1 · <- 4D pin 9 C0 7 $ROWC1 /$V128L B4 11 /$V128L $FLIPC · <- 1F pin 12 A4 12 $FLIPC $FLIPC · <- 1F pin 12 A3 14 $FLIPC /$V64L B3 15 /$V64L $RW32 S2 1 $RW32 $RW16 S1 4 $RW16 $RW128 S4 10 $RW128 $RW64 S3 13 $RW64 GND:8=GND VCC:16=+5V 4E — 74LS283: Row adder stage 2, low nibble (283): sprite Y low (Va0-Va3) + stage-1 sum ($RW1-$RW8), no carry in. Sums -> 6D XORs -> VB0-VB3, the row within the sprite. Carry -> 5E. — verified 2026-07-26 4E ✓ 74LS283 $RW2 · <- 4D sum (stage 1) B2 2 $RW2 Va1 · <- 5F latch (sprite Y low nibble) | Capcom writes this with a Greek letter; we spell it lowercase A2 3 Va1 Va0 · <- 5F latch (sprite Y low nibble) | Capcom writes this with a Greek letter; we spell it lowercase A1 5 Va0 $RW1 · <- 4D sum (stage 1) B1 6 $RW1 GND · no carry in C0 7 GND $RW8 · <- 4D sum (stage 1) B4 11 $RW8 Va3 · <- 5F latch (sprite Y low nibble) | Capcom writes this with a Greek letter; we spell it lowercase A4 12 Va3 Va2 · <- 5F latch (sprite Y low nibble) | Capcom writes this with a Greek letter; we spell it lowercase A3 14 Va2 $RW4 · <- 4D sum (stage 1) B3 15 $RW4 $RWS2 · -> 6D flip XORs -> VB0-VB3 S2 1 $RWS2 $RWS1 · -> 6D flip XORs -> VB0-VB3 S1 4 $RWS1 $ROWC2 · -> 5E pin 7 C4 9 $ROWC2 $RWS8 · -> 6D flip XORs -> VB0-VB3 S4 10 $RWS8 $RWS4 · -> 6D flip XORs -> VB0-VB3 S3 13 $RWS4 GND:8=GND VCC:16=+5V 5E — 74LS283: Row adder stage 2, high nibble (283): sprite Y high (Va4-Va7) + $RW16-$RW128, carry from 4E. Because stage 1 negates the scanline, this computes Va - V; when the high nibble comes out all-ones the scanline falls inside the sprite 16 rows, which 2E detects as VINZONE. C4 unused. — verified 2026-07-26 5E ✓ 74LS283 $RW32 · <- 5D sum (stage 1) B2 2 $RW32 Va5 · <- 5F latch (sprite Y high nibble) | Capcom writes this with a Greek letter; we spell it lowercase A2 3 Va5 Va4 · <- 5F latch (sprite Y high nibble) | Capcom writes this with a Greek letter; we spell it lowercase A1 5 Va4 $RW16 · <- 5D sum (stage 1) B1 6 $RW16 $ROWC2 · <- 4E pin 9 C0 7 $ROWC2 $RW128 · <- 5D sum (stage 1) B4 11 $RW128 Va7 · <- 5F latch (sprite Y high nibble) | Capcom writes this with a Greek letter; we spell it lowercase A4 12 Va7 Va6 · <- 5F latch (sprite Y high nibble) | Capcom writes this with a Greek letter; we spell it lowercase A3 14 Va6 $RW64 · <- 5D sum (stage 1) B3 15 $RW64 LVb5 · -> 2E (all four high = line inside the sprite) | Capcom writes this with a Greek letter; we spell it lowercase S2 1 LVb5 LVb4 · -> 2E (all four high = line inside the sprite) | Capcom writes this with a Greek letter; we spell it lowercase S1 4 LVb4 LVb7 · -> 2E (all four high = line inside the sprite) | Capcom writes this with a Greek letter; we spell it lowercase S4 10 LVb7 LVb6 · -> 2E (all four high = line inside the sprite) | Capcom writes this with a Greek letter; we spell it lowercase S3 13 LVb6 GND:8=GND VCC:16=+5V 2E — 74LS20: Line-in-zone detect (20): the four stage-2 high sums LVB4-LVB7 all high means the scanline falls inside this sprite 16 rows -> /VINZONE to 4/6. Second gate not drawn on this sheet. — verified 2026-07-26 2E ✓ 74LS20 LVb5 · <- 5E sum (stage-2 high nibble) | Capcom writes this with a Greek letter; we spell it lowercase C 1 LVb5 LVb7 · <- 5E sum (stage-2 high nibble) | Capcom writes this with a Greek letter; we spell it lowercase A 2 LVb7 LVb4 · <- 5E sum (stage-2 high nibble) | Capcom writes this with a Greek letter; we spell it lowercase D 4 LVb4 LVb6 · <- 5E sum (stage-2 high nibble) | Capcom writes this with a Greek letter; we spell it lowercase B 5 LVb6 /VINZONE · -> 4/6: line-in-sprite qualifier Y 6 /VINZONE GND:7=GND VCC:14=+5V 6D — 74LS86: Row flip XORs (86): each stage-2 sum XOR /$OBVFLIP -> VB0-VB3, the row within the 16-line sprite, reversed when the sprite is vertically flipped. Outputs address the sprite ROMs on sheet 4/6. Drawing labels these V-beta-0..3 (Greek beta qualifier); transcribed VB0-VB3. — verified 2026-07-26 6D ✓ 74LS86 OBVFLIP · common flip input on all four XORs B1 1 OBVFLIP $RWS8 · <- 4E stage-2 sum A1 2 $RWS8 $RWS2 · <- 4E stage-2 sum A2 4 $RWS2 OBVFLIP · common flip input on all four XORs B2 5 OBVFLIP $RWS1 · <- 4E stage-2 sum A3 9 $RWS1 OBVFLIP · common flip input on all four XORs B3 10 OBVFLIP $RWS4 · <- 4E stage-2 sum A4 12 $RWS4 OBVFLIP · common flip input on all four XORs B4 13 OBVFLIP Vb3 · -> 4/6 and the sprite ROM row address (7E/7H on 4/6) | Capcom writes this with a Greek letter; we spell it lowercase Y1 3 Vb3 Vb1 · -> 4/6 and the sprite ROM row address (7E/7H on 4/6) | Capcom writes this with a Greek letter; we spell it lowercase Y2 6 Vb1 Vb0 · -> 4/6 and the sprite ROM row address (7E/7H on 4/6) | Capcom writes this with a Greek letter; we spell it lowercase Y3 8 Vb0 Vb2 · -> 4/6 and the sprite ROM row address (7E/7H on 4/6) | Capcom writes this with a Greek letter; we spell it lowercase Y4 11 Vb2 GND:7=GND VCC:14=+5V 3A — 74LS139: Byte-phase decoder (139, second half): enabled by H8, decodes H2/H4 into the four byte slots of each sprite entry. Y0 -> 3F clock, Y1 -> 3E clock, Y2 = TR2 -> 8B -> the 5F Y-byte latch, Y3 -> 6J pin 13. First half not drawn on this sheet. — verified 2026-07-26 3A ✓ 74LS139 H4 B2 13 H4 H2 A2 14 H2 H8 · decoder enable ~G2 15 H8 /$PH3 · -> 6J pin 13 Y3 9 /$PH3 TR2 · -> 8B pin 2 -> 5F Y-byte latch enable Y2 10 TR2 /$PH1 · -> 3E pin 11 (CLK) Y1 11 /$PH1 /$PH0 · -> 3F pin 11 (CLK) Y0 12 /$PH0 GND:8=GND VCC:16=+5V 3F — 74LS273: Code-byte latch stage 1 (273): DF0-DF7 captured on /$PH0 (3A pin 12), the byte-0 slot of the sprite entry. ~CL tied +5. Outputs feed 3E. — verified 2026-07-27 3F ✓ 74LS273 +5V · never cleared ~CL 1 +5V DF0 · <- playback DF bus D1 3 DF0 DF1 · <- playback DF bus D2 4 DF1 DF2 · <- playback DF bus D3 7 DF2 DF3 · <- playback DF bus D4 8 DF3 /$PH0 CLK 11 /$PH0 DF4 · <- playback DF bus D5 13 DF4 DF5 · <- playback DF bus D6 14 DF5 DF6 · <- playback DF bus D7 17 DF6 DF7 · <- playback DF bus D8 18 DF7 $CP0B · -> 3E (stage 2) Q1 2 $CP0B $CP1B · -> 3E (stage 2) Q2 5 $CP1B $CP2B · -> 3E (stage 2) Q3 6 $CP2B $CP3B · -> 3E (stage 2) Q4 9 $CP3B $CP4B · -> 3E (stage 2) Q5 12 $CP4B $CP5B · -> 3E (stage 2) Q6 15 $CP5B $CP6B · -> 3E (stage 2) Q7 16 $CP6B $CP7B · -> 3E (stage 2) Q8 19 $CP7B GND:10=GND VCC:20=+5V 3E — 74LS273: Code-byte latch stage 2 (273): re-latches the 3F outputs on /$PH1 (3A pin 11) -> AD0-AD7, the sprite code low byte to sheet 4/6. ~CL tied +5. The apparent bit crossover between 3F and 3E is only the 273 pin interleave (D and Q alternate down each side) - the wiring runs straight across. — verified 2026-07-27 3E ✓ 74LS273 +5V · never cleared ~CL 1 +5V $CP3B · <- 3F pin 9 D1 3 $CP3B $CP2B · <- 3F pin 6 D2 4 $CP2B $CP1B · <- 3F pin 5 D3 7 $CP1B $CP0B · <- 3F pin 2 D4 8 $CP0B /$PH1 · <- 3A pin 11 CLK 11 /$PH1 $CP7B · <- 3F pin 19 D5 13 $CP7B $CP6B · <- 3F pin 16 D6 14 $CP6B $CP5B · <- 3F pin 15 D7 17 $CP5B $CP4B · <- 3F pin 12 D8 18 $CP4B AD3 · -> 4/6 sprite code low byte Q1 2 AD3 AD2 · -> 4/6 sprite code low byte Q2 5 AD2 AD1 · -> 4/6 sprite code low byte Q3 6 AD1 AD0 · -> 4/6 sprite code low byte Q4 9 AD0 AD7 · -> 4/6 sprite code low byte Q5 12 AD7 AD6 · -> 4/6 sprite code low byte Q6 15 AD6 AD5 · -> 4/6 sprite code low byte Q7 16 AD5 AD4 · -> 4/6 sprite code low byte Q8 19 AD4 GND:10=GND VCC:20=+5V 4F — 74LS273: Attribute latch (273): DF0-DF7 captured on /$PH1 (same clock as 3E). Outputs split the attribute byte - AD8/AD9 code bank bits (pins 16,19) to 4/6; HOVER sprite X msb (pin 2) to 5/6+6/6; /$OBHFLIP (pin 6) to 2F pin 13 and 1F pin 5; /$OBVFLIP (pin 9) via 1F to the 6D row XORs; $COL4P/COL5P (pins 12,15) to 2F. Q2 (pin 5) unused. — verified 2026-07-27 4F ✓ 74LS273 +5V · never cleared ~CL 1 +5V DF0 · <- playback DF bus D1 3 DF0 DF1 · <- playback DF bus D2 4 DF1 DF2 · <- playback DF bus D3 7 DF2 DF3 · <- playback DF bus D4 8 DF3 /$PH1 · <- 3A pin 11 (same clock as 3E) CLK 11 /$PH1 DF4 · <- playback DF bus D5 13 DF4 DF5 · <- playback DF bus D6 14 DF5 DF6 · <- playback DF bus D7 17 DF6 DF7 · <- playback DF bus D8 18 DF7 HOVER · -> 5/6 and 6/6 (sprite X msb) Q1 2 HOVER OBHFLIP · -> 2F pin 13 and 1F pin 5 Q3 6 OBHFLIP /$OBVFLIP · -> 1F pin 3, inverted there to make /$OBVFLIP Q4 9 /$OBVFLIP $COL4P · -> 2F pin 4 Q5 12 $COL4P $COL5P · -> 2F pin 6 Q6 15 $COL5P AD8 · -> 4/6 Q7 16 AD8 AD9 · -> 4/6 (code bank high) Q8 19 AD9 GND:10=GND VCC:20=+5V 2F — 74LS174: Attribute re-latch (174) clocked by OH from 4/6, ~CL tied +5. Three flip-flops used: $COL4P->COL4 (pins 4->5) and $COL5P->COL5 (6->7), both to 5/6 and 6/6 for the sprite palette; /$OBHFLIP->OBHFLIPa (13->12) to 4/6. The other three flip-flops are not drawn. — verified 2026-07-27 2F ✓ 74LS174 +5V · never cleared ~CL 1 +5V $COL4P · <- 4F pin 12 D2 4 $COL4P $COL5P · <- 4F pin 15 D3 6 $COL5P OH · <- 4/6 CLK 9 OH OBHFLIP · <- 4F pin 6 (also to 1F pin 5) D5 13 OBHFLIP COL4 · -> 5/6 and 6/6 Q2 5 COL4 COL5 · -> 5/6 and 6/6 Q3 7 COL5 OBHFLIPa · -> 4/6 Q5 12 OBHFLIPa GND:8=GND VCC:16=+5V 1F — 74LS04: Hex inverter (04), three gates drawn. 3->4: /$OBVFLIP from 4F -> /$OBVFLIP to the 6D row XORs. 5->6: /$OBHFLIP -> /$OBHFLIP to 9D. 13->12: the global FLIP from 1/6 -> $FLIPC, which drives the A inputs of both stage-1 row adders and so switches the vertical offset in cocktail mode. — verified 2026-07-27 1F ✓ 74LS04 /$OBVFLIP · <- 4F pin 9 A2 3 /$OBVFLIP OBHFLIP · <- 4F pin 6 A3 5 OBHFLIP FLIP · <- 1/6 (global screen flip) A6 13 FLIP OBVFLIP · -> the four 6D row XORs Y2 4 OBVFLIP /$OBHFLIP · -> 9D pin 2 Y3 6 /$OBHFLIP $FLIPC · inverted FLIP -> 4D pins 3,14,12 and 5D pins 5,3,14,12 (row-offset constant) Y6 12 $FLIPC GND:7=GND VCC:14=+5V 9D — 74LS86: Column-phase flip XORs (86), two gates drawn and CASCADED: OBH4 = H4 XOR /$OBHFLIP (pins 1,2 -> 3); OBH8 = H8 XOR OBH4 (pins 5,4 -> 6), with pin 4 fed from pin 3. Both outputs go to 4/6 as the flipped column phases. Other two gates not drawn here. — verified 2026-07-27 9D ✓ 74LS86 H4 · column phase B1 1 H4 /$OBHFLIP · <- 1F pin 6 A1 2 /$OBHFLIP OBH4 · <- 9D pin 3 (cascaded from gate 1) A2 4 OBH4 H8 · column phase B2 5 H8 OBH4 · -> 4/6 (flipped column phase) Y1 3 OBH4 OBH8 · -> 4/6 (flipped column phase) Y2 6 OBH8 GND:7=GND VCC:14=+5V 6J — 74LS00: Phase-strobe gating (00), two gates drawn and chained: gate 4 has pin 12 tied +5 so it inverts /$PH3 (3A pin 9) -> /$PH3 on pin 11, which feeds gate 3 pin 10; gate 3 NANDs that with H1 -> /TR3 (pin 8) to 4/6. Gates 1 and 2 not drawn here. — verified 2026-07-27 6J ✓ 74LS00 H1 A3 9 H1 $PH3 · <- 6J pin 11 B3 10 $PH3 +5V · tied high - gate 4 acts as an inverter A4 12 +5V /$PH3 · <- 3A pin 9 B4 13 /$PH3 /TR3 · -> 4/6 Y3 8 /TR3 $PH3 · -> 6J pin 10 Y4 11 $PH3 GND:7=GND VCC:14=+5V 8B — 74LS00: One NAND of the 00 drawn here: pin 1 tied +5 so the gate inverts TR2 -> $VALATCH (pin 3), the latch enable for the 5F sprite-Y register. Other gates not drawn on this sheet. — verified 2026-07-26 8B ✓ 74LS00 +5V · tied high - gate acts as an inverter A1 1 +5V TR2 · <- 3A pin 10 B1 2 TR2 drawn on b1-2-objcontroller - click to jump there · $SEQ8B3 · <- 8B pin 8 (gate 3 output) A2 4 $SEQ8B3 ↗ drawn on b1-2-objcontroller - click to jump there · /HINITB · <- CN-2 C18 (A-board 2N pin 2); also to 10B pin 10 B2 5 /HINITB ↗ drawn on b1-2-objcontroller - click to jump there · $SEQ8A3 · <- 8A pin 8 A3 9 $SEQ8A3 ↗ drawn on b1-2-objcontroller - click to jump there · /OVER96 · <- 8B pin 11 (gate 4 output); overbar confirmed on the sheet (Robert, 2026-07-27) B3 10 /OVER96 ↗ drawn on b1-2-objcontroller - click to jump there · OB7 · <- 7A pin 13 A4 12 OB7 ↗ drawn on b1-2-objcontroller - click to jump there · OB8 · <- 7A pin 12 (Robert read 2026-07-26) B4 13 OB8 ↗ $VALATCH · -> 5F pin 11 (latches the sprite Y byte) Y1 3 $VALATCH drawn on b1-2-objcontroller - click to jump there · $SEQ8B · -> 8A pin 1 Y2 6 $SEQ8B ↗ drawn on b1-2-objcontroller - click to jump there · $SEQ8B3 · -> 8B pin 4 Y3 8 $SEQ8B3 ↗ drawn on b1-2-objcontroller - click to jump there · /OVER96 · -> 1/6 (6B pin 4 + 5B pin 3): ends the 96-object scan Y4 11 /OVER96 ↗ GND:7=GND VCC:14=+5V
· Original scan — manual p34 · zoom
original schematic scan
1H
2H
4H
3H
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5F
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