85605-B-1 Sheet 4/6 — OBJECT ROM

manual p35 · 22 ICs · 22 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Interboard connectors (the band cables between the boards) — circled letter+number labels on the drawing are connector row + pin
7K — 74LS139: Dual decoder (139). Half 1: ~G1 grounded, AD8/AD9 -> four bank selects /$BANK0-3 to the E and H ROM stacks (bank 3 = the empty 10E/10H sockets). Half 2: ~G2 from 6F pin 2, A2 = /$V1a (6F pin 5), B2 from 8K pin 11 -> Y0 (pin 12) = /2ST to 6/6 and Y1 (pin 11) = /1ST to 5/6, the line-buffer output strobes. Y2/Y3 (pins 10, 9) not drawn on this sheet - parked. Only two of the four outputs of this decoder half are used (/1ST and /2ST); pins 9 and 10 are drawn nowhere and have no tracks on the board. — verified 2026-07-27 7K ✓ 74LS139 GND · always enabled ~G1 1 GND AD8 A1 2 AD8 AD9 B1 3 AD9 $6MB · <- 8K pin 11; also 8K pin 10 and 9K pin 11 B2 13 $6MB V1a · <- 6F pin 5; also 6H.2, 9K.13, 6A.1, and out to 5/6 (drawn V1-alpha) A2 14 V1a $BUFPH · <- 6F pin 2 ~G2 15 $BUFPH /$BANK0 · -> 7E and 7H pin 20 Y0 4 /$BANK0 /$BANK1 · -> 8E and 8H pin 20 Y1 5 /$BANK1 /$BANK2 · -> 9E and 9H pin 20 Y2 6 /$BANK2 /$BANK3 · -> 10E and 10H pin 20 Y3 7 /$BANK3 /1ST · -> 5/6 | drawing labels this output "1" Y1 11 /1ST /2ST · -> 6/6 | drawing labels this output "0" Y0 12 /2ST GND:8=GND VCC:16=+5V 7E — 27128: Sprite ROM 7E, planes Z+Y (27128). Address: sprite code AD7-AD0 on A13-A6, column phase OBH8/OBH4 on A5/A0, row V-beta-3..0 on A4-A1. ~OE grounded; VPP//PGM/VCC +5. ~CE from 7K pin 4, shared with the H-stack partner. — verified 2026-07-27 7E ✓ 27128 AD6 · sprite code A12 2 AD6 AD1 · sprite code A7 3 AD1 AD0 · sprite code A6 4 AD0 OBH8 · column phase (3/6 9D) A5 5 OBH8 Vb3 · row, drawn V-beta-3 | Capcom writes this with a Greek letter; we spell it lowercase A4 6 Vb3 Vb2 · row, V-beta-2 | Capcom writes this with a Greek letter; we spell it lowercase A3 7 Vb2 Vb1 · row, V-beta-1 | Capcom writes this with a Greek letter; we spell it lowercase A2 8 Vb1 Vb0 · row, V-beta-0 | Capcom writes this with a Greek letter; we spell it lowercase A1 9 Vb0 OBH4 · column phase (3/6 9D) A0 10 OBH4 /$BANK0 · <- 7K pin 4 (shared with the H-stack partner) ~CE 20 /$BANK0 AD4 · sprite code A10 21 AD4 GND · tied low ~OE 22 GND AD5 · sprite code A11 23 AD5 AD3 · sprite code A9 24 AD3 AD2 · sprite code A8 25 AD2 AD7 · sprite code A13 26 AD7 $OY0 · plane Y D0 11 $OY0 $OY1 · plane Y D1 12 $OY1 $OY2 · plane Y D2 13 $OY2 $OY3 · plane Y D3 15 $OY3 $OZ0 · plane Z D4 16 $OZ0 $OZ1 · plane Z D5 17 $OZ1 $OZ2 · plane Z D6 18 $OZ2 $OZ3 · plane Z D7 19 $OZ3 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 8E — 27128: Sprite ROM 8E, planes Z+Y (27128). Address: sprite code AD7-AD0 on A13-A6, column phase OBH8/OBH4 on A5/A0, row V-beta-3..0 on A4-A1. ~OE grounded; VPP//PGM/VCC +5. ~CE from 7K pin 5, shared with the H-stack partner. — verified 2026-07-27 8E ✓ 27128 AD6 · sprite code A12 2 AD6 AD1 · sprite code A7 3 AD1 AD0 · sprite code A6 4 AD0 OBH8 · column phase (3/6 9D) A5 5 OBH8 Vb3 · row, drawn V-beta-3 | Capcom writes this with a Greek letter; we spell it lowercase A4 6 Vb3 Vb2 · row, V-beta-2 | Capcom writes this with a Greek letter; we spell it lowercase A3 7 Vb2 Vb1 · row, V-beta-1 | Capcom writes this with a Greek letter; we spell it lowercase A2 8 Vb1 Vb0 · row, V-beta-0 | Capcom writes this with a Greek letter; we spell it lowercase A1 9 Vb0 OBH4 · column phase (3/6 9D) A0 10 OBH4 /$BANK1 · <- 7K pin 5 (shared with the H-stack partner) ~CE 20 /$BANK1 AD4 · sprite code A10 21 AD4 GND · tied low ~OE 22 GND AD5 · sprite code A11 23 AD5 AD3 · sprite code A9 24 AD3 AD2 · sprite code A8 25 AD2 AD7 · sprite code A13 26 AD7 $OY0 · plane Y D0 11 $OY0 $OY1 · plane Y D1 12 $OY1 $OY2 · plane Y D2 13 $OY2 $OY3 · plane Y D3 15 $OY3 $OZ0 · plane Z D4 16 $OZ0 $OZ1 · plane Z D5 17 $OZ1 $OZ2 · plane Z D6 18 $OZ2 $OZ3 · plane Z D7 19 $OZ3 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 9E — 27128: Sprite ROM 9E, planes Z+Y (27128). Address: sprite code AD7-AD0 on A13-A6, column phase OBH8/OBH4 on A5/A0, row V-beta-3..0 on A4-A1. ~OE grounded; VPP//PGM/VCC +5. ~CE from 7K pin 6, shared with the H-stack partner. — verified 2026-07-27 9E ✓ 27128 AD6 · sprite code A12 2 AD6 AD1 · sprite code A7 3 AD1 AD0 · sprite code A6 4 AD0 OBH8 · column phase (3/6 9D) A5 5 OBH8 Vb3 · row, drawn V-beta-3 | Capcom writes this with a Greek letter; we spell it lowercase A4 6 Vb3 Vb2 · row, V-beta-2 | Capcom writes this with a Greek letter; we spell it lowercase A3 7 Vb2 Vb1 · row, V-beta-1 | Capcom writes this with a Greek letter; we spell it lowercase A2 8 Vb1 Vb0 · row, V-beta-0 | Capcom writes this with a Greek letter; we spell it lowercase A1 9 Vb0 OBH4 · column phase (3/6 9D) A0 10 OBH4 /$BANK2 · <- 7K pin 6 (shared with the H-stack partner) ~CE 20 /$BANK2 AD4 · sprite code A10 21 AD4 GND · tied low ~OE 22 GND AD5 · sprite code A11 23 AD5 AD3 · sprite code A9 24 AD3 AD2 · sprite code A8 25 AD2 AD7 · sprite code A13 26 AD7 $OY0 · plane Y D0 11 $OY0 $OY1 · plane Y D1 12 $OY1 $OY2 · plane Y D2 13 $OY2 $OY3 · plane Y D3 15 $OY3 $OZ0 · plane Z D4 16 $OZ0 $OZ1 · plane Z D5 17 $OZ1 $OZ2 · plane Z D6 18 $OZ2 $OZ3 · plane Z D7 19 $OZ3 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 10E — 27128: EMPTY SOCKET (decoded bank 3, never populated). Sprite ROM 10E, planes Z+Y (27128). Address: sprite code AD7-AD0 on A13-A6, column phase OBH8/OBH4 on A5/A0, row V-beta-3..0 on A4-A1. ~OE grounded; VPP//PGM/VCC +5. ~CE from 7K pin 7, shared with the H-stack partner. — verified 2026-07-27 10E ✓ 27128 AD6 · sprite code A12 2 AD6 AD1 · sprite code A7 3 AD1 AD0 · sprite code A6 4 AD0 OBH8 · column phase (3/6 9D) A5 5 OBH8 Vb3 · row, drawn V-beta-3 | Capcom writes this with a Greek letter; we spell it lowercase A4 6 Vb3 Vb2 · row, V-beta-2 | Capcom writes this with a Greek letter; we spell it lowercase A3 7 Vb2 Vb1 · row, V-beta-1 | Capcom writes this with a Greek letter; we spell it lowercase A2 8 Vb1 Vb0 · row, V-beta-0 | Capcom writes this with a Greek letter; we spell it lowercase A1 9 Vb0 OBH4 · column phase (3/6 9D) A0 10 OBH4 /$BANK3 · <- 7K pin 7 (shared with the H-stack partner) ~CE 20 /$BANK3 AD4 · sprite code A10 21 AD4 GND · tied low ~OE 22 GND AD5 · sprite code A11 23 AD5 AD3 · sprite code A9 24 AD3 AD2 · sprite code A8 25 AD2 AD7 · sprite code A13 26 AD7 $OY0 · plane Y D0 11 $OY0 $OY1 · plane Y D1 12 $OY1 $OY2 · plane Y D2 13 $OY2 $OY3 · plane Y D3 15 $OY3 $OZ0 · plane Z D4 16 $OZ0 $OZ1 · plane Z D5 17 $OZ1 $OZ2 · plane Z D6 18 $OZ2 $OZ3 · plane Z D7 19 $OZ3 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 7H — 27128: Sprite ROM 7H, planes X+W (27128). Address: sprite code AD7-AD0 on A13-A6, column phase OBH8/OBH4 on A5/A0, row V-beta-3..0 on A4-A1. ~OE grounded; VPP//PGM/VCC +5. ~CE from 7K pin 4, shared with the E-stack partner. — verified 2026-07-27 7H ✓ 27128 AD6 · sprite code A12 2 AD6 AD1 · sprite code A7 3 AD1 AD0 · sprite code A6 4 AD0 OBH8 · column phase (3/6 9D) A5 5 OBH8 Vb3 · row, drawn V-beta-3 | Capcom writes this with a Greek letter; we spell it lowercase A4 6 Vb3 Vb2 · row, V-beta-2 | Capcom writes this with a Greek letter; we spell it lowercase A3 7 Vb2 Vb1 · row, V-beta-1 | Capcom writes this with a Greek letter; we spell it lowercase A2 8 Vb1 Vb0 · row, V-beta-0 | Capcom writes this with a Greek letter; we spell it lowercase A1 9 Vb0 OBH4 · column phase (3/6 9D) A0 10 OBH4 /$BANK0 · <- 7K pin 4 (shared with the E-stack partner) ~CE 20 /$BANK0 AD4 · sprite code A10 21 AD4 GND · tied low ~OE 22 GND AD5 · sprite code A11 23 AD5 AD3 · sprite code A9 24 AD3 AD2 · sprite code A8 25 AD2 AD7 · sprite code A13 26 AD7 $OW0 · plane W D0 11 $OW0 $OW1 · plane W D1 12 $OW1 $OW2 · plane W D2 13 $OW2 $OW3 · plane W D3 15 $OW3 $OX0 · plane X D4 16 $OX0 $OX1 · plane X D5 17 $OX1 $OX2 · plane X D6 18 $OX2 $OX3 · plane X D7 19 $OX3 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 8H — 27128: Sprite ROM 8H, planes X+W (27128). Address: sprite code AD7-AD0 on A13-A6, column phase OBH8/OBH4 on A5/A0, row V-beta-3..0 on A4-A1. ~OE grounded; VPP//PGM/VCC +5. ~CE from 7K pin 5, shared with the E-stack partner. — verified 2026-07-27 8H ✓ 27128 AD6 · sprite code A12 2 AD6 AD1 · sprite code A7 3 AD1 AD0 · sprite code A6 4 AD0 OBH8 · column phase (3/6 9D) A5 5 OBH8 Vb3 · row, drawn V-beta-3 | Capcom writes this with a Greek letter; we spell it lowercase A4 6 Vb3 Vb2 · row, V-beta-2 | Capcom writes this with a Greek letter; we spell it lowercase A3 7 Vb2 Vb1 · row, V-beta-1 | Capcom writes this with a Greek letter; we spell it lowercase A2 8 Vb1 Vb0 · row, V-beta-0 | Capcom writes this with a Greek letter; we spell it lowercase A1 9 Vb0 OBH4 · column phase (3/6 9D) A0 10 OBH4 /$BANK1 · <- 7K pin 5 (shared with the E-stack partner) ~CE 20 /$BANK1 AD4 · sprite code A10 21 AD4 GND · tied low ~OE 22 GND AD5 · sprite code A11 23 AD5 AD3 · sprite code A9 24 AD3 AD2 · sprite code A8 25 AD2 AD7 · sprite code A13 26 AD7 $OW0 · plane W D0 11 $OW0 $OW1 · plane W D1 12 $OW1 $OW2 · plane W D2 13 $OW2 $OW3 · plane W D3 15 $OW3 $OX0 · plane X D4 16 $OX0 $OX1 · plane X D5 17 $OX1 $OX2 · plane X D6 18 $OX2 $OX3 · plane X D7 19 $OX3 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 9H — 27128: Sprite ROM 9H, planes X+W (27128). Address: sprite code AD7-AD0 on A13-A6, column phase OBH8/OBH4 on A5/A0, row V-beta-3..0 on A4-A1. ~OE grounded; VPP//PGM/VCC +5. ~CE from 7K pin 6, shared with the E-stack partner. — verified 2026-07-27 9H ✓ 27128 AD6 · sprite code A12 2 AD6 AD1 · sprite code A7 3 AD1 AD0 · sprite code A6 4 AD0 OBH8 · column phase (3/6 9D) A5 5 OBH8 Vb3 · row, drawn V-beta-3 | Capcom writes this with a Greek letter; we spell it lowercase A4 6 Vb3 Vb2 · row, V-beta-2 | Capcom writes this with a Greek letter; we spell it lowercase A3 7 Vb2 Vb1 · row, V-beta-1 | Capcom writes this with a Greek letter; we spell it lowercase A2 8 Vb1 Vb0 · row, V-beta-0 | Capcom writes this with a Greek letter; we spell it lowercase A1 9 Vb0 OBH4 · column phase (3/6 9D) A0 10 OBH4 /$BANK2 · <- 7K pin 6 (shared with the E-stack partner) ~CE 20 /$BANK2 AD4 · sprite code A10 21 AD4 GND · tied low ~OE 22 GND AD5 · sprite code A11 23 AD5 AD3 · sprite code A9 24 AD3 AD2 · sprite code A8 25 AD2 AD7 · sprite code A13 26 AD7 $OW0 · plane W D0 11 $OW0 $OW1 · plane W D1 12 $OW1 $OW2 · plane W D2 13 $OW2 $OW3 · plane W D3 15 $OW3 $OX0 · plane X D4 16 $OX0 $OX1 · plane X D5 17 $OX1 $OX2 · plane X D6 18 $OX2 $OX3 · plane X D7 19 $OX3 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 10H — 27128: EMPTY SOCKET (decoded bank 3, never populated). Sprite ROM 10H, planes X+W (27128). Address: sprite code AD7-AD0 on A13-A6, column phase OBH8/OBH4 on A5/A0, row V-beta-3..0 on A4-A1. ~OE grounded; VPP//PGM/VCC +5. ~CE from 7K pin 7, shared with the E-stack partner. — verified 2026-07-27 10H ✓ 27128 AD6 · sprite code A12 2 AD6 AD1 · sprite code A7 3 AD1 AD0 · sprite code A6 4 AD0 OBH8 · column phase (3/6 9D) A5 5 OBH8 Vb3 · row, drawn V-beta-3 | Capcom writes this with a Greek letter; we spell it lowercase A4 6 Vb3 Vb2 · row, V-beta-2 | Capcom writes this with a Greek letter; we spell it lowercase A3 7 Vb2 Vb1 · row, V-beta-1 | Capcom writes this with a Greek letter; we spell it lowercase A2 8 Vb1 Vb0 · row, V-beta-0 | Capcom writes this with a Greek letter; we spell it lowercase A1 9 Vb0 OBH4 · column phase (3/6 9D) A0 10 OBH4 /$BANK3 · <- 7K pin 7 (shared with the E-stack partner) ~CE 20 /$BANK3 AD4 · sprite code A10 21 AD4 GND · tied low ~OE 22 GND AD5 · sprite code A11 23 AD5 AD3 · sprite code A9 24 AD3 AD2 · sprite code A8 25 AD2 AD7 · sprite code A13 26 AD7 $OW0 · plane W D0 11 $OW0 $OW1 · plane W D1 12 $OW1 $OW2 · plane W D2 13 $OW2 $OW3 · plane W D3 15 $OW3 $OX0 · plane X D4 16 $OX0 $OX1 · plane X D5 17 $OX1 $OX2 · plane X D6 18 $OX2 $OX3 · plane X D7 19 $OX3 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 7J — 74LS194A: Z-plane pixel shifter (194): loads 7E/8E/9E D7-D4 on 4-3H, then shifts left or right per the sprite H-flip. QA (normal) and QD (flipped) both go to the 10K tap mux. ~CL +5, both serial inputs grounded, clocked by OB6M. — verified 2026-07-27 7J ✓ 74LS194A +5V · never cleared ~CL 1 +5V GND · serial-right in tied low SR 2 GND $OZ3 · <- 7E/8E/9E D7-D4 A 3 $OZ3 $OZ2 · <- 7E/8E/9E D7-D4 B 4 $OZ2 $OZ1 · <- 7E/8E/9E D7-D4 C 5 $OZ1 $OZ0 · <- 7E/8E/9E D7-D4 D 6 $OZ0 GND · serial-left in tied low SL 7 GND $OBS0 · <- 9C pin 11 S0 9 $OBS0 $OBS1 · <- 8K pin 3 S1 10 $OBS1 $OBSCLK · <- 8K pin 8 CLK 11 $OBSCLK $OZQD · flipped direction -> 10K QD 12 $OZQD $OZQA · normal direction -> 10K QA 15 $OZQA GND:8=GND VCC:16=+5V 8J — 74LS194A: Y-plane pixel shifter (194): loads 7E/8E/9E D3-D0 on 4-3H, then shifts left or right per the sprite H-flip. QA (normal) and QD (flipped) both go to the 10K tap mux. ~CL +5, both serial inputs grounded, clocked by OB6M. — verified 2026-07-27 8J ✓ 74LS194A +5V · never cleared ~CL 1 +5V GND · serial-right in tied low SR 2 GND $OY3 · <- 7E/8E/9E D3-D0 A 3 $OY3 $OY2 · <- 7E/8E/9E D3-D0 B 4 $OY2 $OY1 · <- 7E/8E/9E D3-D0 C 5 $OY1 $OY0 · <- 7E/8E/9E D3-D0 D 6 $OY0 GND · serial-left in tied low SL 7 GND $OBS0 · <- 9C pin 11 S0 9 $OBS0 $OBS1 · <- 8K pin 3 S1 10 $OBS1 $OBSCLK · <- 8K pin 8 CLK 11 $OBSCLK $OYQD · flipped direction -> 10K QD 12 $OYQD $OYQA · normal direction -> 10K QA 15 $OYQA GND:8=GND VCC:16=+5V 9J — 74LS194A: X-plane pixel shifter (194): loads 7H/8H/9H D7-D4 on 4-3H, then shifts left or right per the sprite H-flip. QA (normal) and QD (flipped) both go to the 10K tap mux. ~CL +5, both serial inputs grounded, clocked by OB6M. — verified 2026-07-27 9J ✓ 74LS194A +5V · never cleared ~CL 1 +5V GND · serial-right in tied low SR 2 GND $OX3 · <- 7H/8H/9H D7-D4 A 3 $OX3 $OX2 · <- 7H/8H/9H D7-D4 B 4 $OX2 $OX1 · <- 7H/8H/9H D7-D4 C 5 $OX1 $OX0 · <- 7H/8H/9H D7-D4 D 6 $OX0 GND · serial-left in tied low SL 7 GND $OBS0 · <- 9C pin 11 S0 9 $OBS0 $OBS1 · <- 8K pin 3 S1 10 $OBS1 $OBSCLK · <- 8K pin 8 CLK 11 $OBSCLK $OXQD · flipped direction -> 10K QD 12 $OXQD $OXQA · normal direction -> 10K QA 15 $OXQA GND:8=GND VCC:16=+5V 10J — 74LS194A: W-plane pixel shifter (194): loads 7H/8H/9H D3-D0 on 4-3H, then shifts left or right per the sprite H-flip. QA (normal) and QD (flipped) both go to the 10K tap mux. ~CL +5, both serial inputs grounded, clocked by OB6M. — verified 2026-07-27 10J ✓ 74LS194A +5V · never cleared ~CL 1 +5V GND · serial-right in tied low SR 2 GND $OW3 · <- 7H/8H/9H D3-D0 A 3 $OW3 $OW2 · <- 7H/8H/9H D3-D0 B 4 $OW2 $OW1 · <- 7H/8H/9H D3-D0 C 5 $OW1 $OW0 · <- 7H/8H/9H D3-D0 D 6 $OW0 GND · serial-left in tied low SL 7 GND $OBS0 · <- 9C pin 11 S0 9 $OBS0 $OBS1 · <- 8K pin 3 S1 10 $OBS1 $OBSCLK · <- 8K pin 8 CLK 11 $OBSCLK $OWQD · flipped direction -> 10K QD 12 $OWQD $OWQA · normal direction -> 10K QA 15 $OWQA GND:8=GND VCC:16=+5V 10K — 74LS257: Flip tap mux (257): picks QA (normal) or QD (flipped) from each of the four plane shifters -> COL0-COL3, the 4bpp sprite pixel sent to both line buffers. SEL = /$OBHFLIPa so the same per-sprite H-flip that sets the shift direction also selects which end of the register is tapped. ~ST from 6F pin 10, so the pixel bus is only driven in the active window. — verified 2026-07-27 10K ✓ 74LS257 OBHFLIPa · <- 3/6 2F pin 12 (same net that feeds 9K pin 1) SEL 1 OBHFLIPa $OZQA · <- 7J pin 15 1A 2 $OZQA $OZQD · <- 7J pin 12 1B 3 $OZQD $OYQA · <- 8J pin 15 2A 5 $OYQA $OYQD · <- 8J pin 12 2B 6 $OYQD $OXQD · <- 9J pin 12 3B 10 $OXQD $OXQA · <- 9J pin 15 3A 11 $OXQA $OWQD · <- 10J pin 12 4B 13 $OWQD $OWQA · <- 10J pin 15 4A 14 $OWQA $OBST · <- 6F pin 10 ~ST 15 $OBST COL0 · -> 5/6 and 6/6 (4bpp sprite pixel) 1Y 4 COL0 COL1 · -> 5/6 and 6/6 (4bpp sprite pixel) 2Y 7 COL1 COL2 · -> 5/6 and 6/6 (4bpp sprite pixel) 3Y 9 COL2 COL3 · -> 5/6 and 6/6 (4bpp sprite pixel) 4Y 12 COL3 GND:8=GND VCC:16=+5V 8K — 74LS32: Quad OR (32), all four gates. g1: 4-3H OR /$OBHFLIPa -> $OBS1, the shifter mode bit. g2: V1 OR GND (buffer) -> $LV1D to 6F pin 4 and 6H pin 14. g3 and g4 are a cascaded buffer chain on the 6M pixel clock, each with its second input grounded: 6M -> pin 11 = $6MB (to 7K pin 13 and 9K pin 11) -> pin 8 = OB6M, the clock for all four plane shifters. — verified 2026-07-27 8K ✓ 74LS32 4-3H · <- CN-2 C4 A1 1 4-3H /$OBHFLIPa · <- 9K pin 2 B1 2 /$OBHFLIPa GND · gate acts as a buffer B2 4 GND V1 · <- 1/6 (also to 9K pin 5) A2 5 V1 GND · gate acts as a buffer A3 9 GND $6MB · <- 8K pin 11 B3 10 $6MB GND · gate acts as a buffer A4 12 GND 6M · <- CN-2 C3 B4 13 6M $OBS1 · -> all four shifters pin 10 Y1 3 $OBS1 $LV1D · -> 6F pin 4 and 6H pin 14 Y2 6 $LV1D $OBSCLK · -> 7J/8J/9J/10J pin 11 CLK (unlabelled on the sheet) Y3 8 $OBSCLK $6MB · buffered 6M -> 8K pin 10, 7K pin 13, 9K pin 11 (unlabelled on the sheet) Y4 11 $6MB GND:7=GND VCC:14=+5V 9C — 74LS32: Quad OR. Only gate 4 is drawn on this sheet: 4-3H OR /$OBHFLIPa -> $OBS0, the shifter mode bit that pairs with 8K pin 3 ($OBS1). Gates 1-3 of the same physical chip are drawn on sheet 2/6. — verified 2026-07-27 9C ✓ 74LS32 drawn on b1-2-objcontroller - click to jump there · BLEN · <- 1/6 A1 1 BLEN ↗ drawn on b1-2-objcontroller - click to jump there · /24_96TM · <- 9B pin 6 (also 10B pin 9, 10C pin 12) B1 2 /24_96TM ↗ drawn on b1-2-objcontroller - click to jump there · LV1 · <- 4/6 A2 4 LV1 ↗ drawn on b1-2-objcontroller - click to jump there · 24_96TM · <- 9B pin 5 B2 5 24_96TM ↗ drawn on b1-2-objcontroller - click to jump there · /$LV1 · <- 9D pin 8 A3 9 /$LV1 ↗ drawn on b1-2-objcontroller - click to jump there · 24_96TM · <- 9B pin 5 B3 10 24_96TM ↗ OBHFLIPa · <- 3/6 2F pin 12 A4 12 OBHFLIPa 4-3H · <- CN-2 C4 B4 13 4-3H drawn on b1-2-objcontroller - click to jump there · $SEQ9C1 · -> 6A pin 9 Y1 3 $SEQ9C1 ↗ drawn on b1-2-objcontroller - click to jump there · OBBSEL · -> 3/6 and 1/6 (6B pin 12) Y2 6 OBBSEL ↗ drawn on b1-2-objcontroller - click to jump there · OBASEL · -> 1/6 (6B pin 1) and 3/6 Y3 8 OBASEL ↗ $OBS0 · -> all four shifters pin 9 Y4 11 $OBS0 GND:7=GND VCC:14=+5V 9K — 74LS04: Hex inverter, all six gates used. g1 /$OBHFLIPa -> /$OBHFLIPa (8K pin 2). g2 /$LHBL -> /$LHBL (6H pin 3). g3 V1 -> LV1, the line-buffer alternation, out to 2/6 and 3/6. g6 /$V1a -> /$V1a (6A pin 12). g5 and g4 are the 6M chain: $6MB -> L6MB (pin 10, the line-buffer write clock, to 6J pins 2/4 and off to 5/6 + 6/6) -> OB6M (pin 8, also to 5/6 + 6/6). — verified 2026-07-27 9K ✓ 74LS04 OBHFLIPa · <- 3/6 2F pin 12 A1 1 OBHFLIPa LHBL · <- CN-2 D9 A2 3 LHBL V1 · <- 1/6 (also to 8K pin 5) A3 5 V1 L6MB · <- 9K pin 10 A4 9 L6MB $6MB · <- 8K pin 11 A5 11 $6MB V1a · <- 6F pin 5 A6 13 V1a /$OBHFLIPa · -> 8K pin 2 Y1 2 /$OBHFLIPa /$LHBL · -> 6H pin 3 Y2 4 /$LHBL LV1 · inverted V1 -> out to 2/6 and 3/6 as the line-buffer alternation Y3 6 LV1 OB6M · -> 5/6, 6/6 Y4 8 OB6M L6MB · -> 6J pins 2 and 4, 9K pin 9, and out to 5/6 + 6/6 Y5 10 L6MB /$V1a · -> 6A pin 12 Y6 12 /$V1a GND:7=GND VCC:14=+5V 6E — TBP24S10: Object timing PROM (TBP24S10 / 7611). Address = the V counter V1-V128 from 1/6; both ~CE grounded so it is always enabled. D0/D1 (pins 12, 11) are latched by 6F at OH to make the buffer-phase and display signals; D2 (pin 10) leaves directly as BLTIMING to 2/6, where it sets the 24/96 line phase. D3 (pin 9) unused. This little PROM is what defines the sprite engine line timing. — verified 2026-07-27 6E ✓ TBP24S10 V64 · V counter in, from 1/6 A6 1 V64 V32 · V counter in, from 1/6 A5 2 V32 V16 · V counter in, from 1/6 A4 3 V16 V8 · V counter in, from 1/6 A3 4 V8 V1 · V counter in, from 1/6 A0 5 V1 V2 · V counter in, from 1/6 A1 6 V2 V4 · V counter in, from 1/6 A2 7 V4 GND · ~CE tied low - always enabled ~CE1 13 GND GND · ~CE tied low - always enabled ~CE2 14 GND V128 · V counter in, from 1/6 A7 15 V128 BLTIMING · -> 2/6 directly, not via the latch D2 10 BLTIMING $OTPD1 · -> 6F pin 6 (latched at OH) D1 11 $OTPD1 $OTPD0 · -> 6F pin 3 (latched at OH) D0 12 $OTPD0 GND:8=GND VCC:16=+5V 6F — 74LS174: Line-rate latch (174) clocked by OH (CN-2 D3, which also passes to 3/6); ~CL +5. Latches PROM bits D0/D1 from 6E, an LV1-derived bit from 8K pin 6, and /VINZONE from 3/6 -> $BUFPH (7K enable), /$V1a, /DISPTMa (to 5/6 and 6H), and $OBST (10K output enable). The fifth and sixth flip-flops are not drawn. — verified 2026-07-27 6F ✓ 74LS174 +5V · never cleared ~CL 1 +5V $OTPD0 · <- 6E pin 12 (PROM D0) D1 3 $OTPD0 $LV1D · <- 8K pin 6 D2 4 $LV1D $OTPD1 · <- 6E pin 11 (PROM D1) D3 6 $OTPD1 OH · <- CN-2 D3; the same line also goes out to 3/6 (2F pin 9) CLK 9 OH /VINZONE · <- 3/6 (2E pin 6) D4 11 /VINZONE $BUFPH · -> 7K pin 15 Q1 2 $BUFPH V1a · -> 7K.14, 6H.2, 9K.13, 6A.1, and 5/6 Q2 5 V1a /DISPTMa · -> 5/6, and 6H pin 1 (~EN) | name joined 2026-07-27: sheet 4/6 letters it without a bar, 5/6 with one Q3 7 /DISPTMa $OBST · -> 10K pin 15 (~ST), confirmed Q4 10 $OBST GND:8=GND VCC:16=+5V 6H — 74LS139: Line-buffer strobe decoder (139) - the chip whose faulty pin 6 caused the striped sprites. Half 1: ~G1 = /DISPTMa (6F pin 7), A1 = /$V1a (6F pin 5), B1 = /$LHBL (9K pin 4) -> Y2 (pin 6) = /1CL and Y3 (pin 7) = /2CL, the per-buffer clear windows, which also feed 6J to make /1WR and /2WR. Half 2: ~G2 = the 6E PROM D0 bit, A2 = $LV1D (8K pin 6), B2 = /TR3 from 3/6 -> Y0 (pin 12) = /2LOAD to 6/6 and Y1 (pin 11) = /1LOAD to 5/6. Outputs 4, 5, 9, 10 not drawn. — verified 2026-07-27 6H ✓ 74LS139 /DISPTMa · <- 6F pin 7 | name joined 2026-07-27: sheet 4/6 letters it without a bar, 5/6 with one ~G1 1 /DISPTMa V1a · <- 6F pin 5 A1 2 V1a /$LHBL · <- 9K pin 4 B1 3 /$LHBL /TR3 · <- 3/6 (6J pin 8) B2 13 /TR3 $LV1D · <- 8K pin 6 (same net as 6F pin 4) A2 14 $LV1D $OTPD0 · <- 6E pin 12 (same PROM bit that feeds 6F pin 3) ~G2 15 $OTPD0 /1CL · drawing labels this output 2; -> 5/6 and 6J pin 5 Y2 6 /1CL /2CL · drawing labels this output 3; -> 6/6 and 6J pin 1 Y3 7 /2CL /1LOAD · drawing labels this output 1; to 5/6 Y1b 11 /1LOAD /2LOAD · drawing labels this output 0; to 6/6 Y0b 12 /2LOAD GND:8=GND VCC:16=+5V 6J — 74LS00: Write-strobe NANDs (00), two gates drawn: each takes a buffer clear window from 6H and NANDs it with WRPH (9K pin 10) -> /2WR (pin 3) to 6/6 and /1WR (pin 6) to 5/6. The other two gates are not drawn here. — verified 2026-07-27 6J ✓ 74LS00 /2CL · <- 6H pin 7 A1 1 /2CL L6MB · <- 9K pin 10 (shared with 6J pin 4) B1 2 L6MB L6MB · <- 9K pin 10 (shared with 6J pin 2) A2 4 L6MB /1CL · <- 6H pin 6 B2 5 /1CL /2WR · to 6/6 Y1 3 /2WR /1WR · to 5/6 Y2 6 /1WR GND:7=GND VCC:14=+5V 6A — 74LS08: Quad AND. The two gates here split FLIP between the two line buffers: OBFLIP2 = /$V1a AND FLIP (to 6/6), OBFLIP1 = /$V1a AND FLIP (to 5/6), with /$V1a from 9K pin 12. Each buffer therefore sees FLIP only on the lines it owns. The other two gates are on sheets 1/6 and 2/6. — verified 2026-07-27 6A ✓ 74LS08 V1a · <- 6F pin 5 A1 1 V1a FLIP · <- 1/6 B1 2 FLIP drawn on b1-1-objram - click to jump there · /ACL1 · <- CN-1 B19 (drawn ACL2 on this sheet; same wire as A-board /ACL1) A2 4 /ACL1 ↗ drawn on b1-1-objram - click to jump there · $DMAEND · <- 6B pin 6 B2 5 $DMAEND ↗ drawn on b1-2-objcontroller - click to jump there · $SEQ9C1 · <- 9C pin 3 A3 9 $SEQ9C1 ↗ drawn on b1-2-objcontroller - click to jump there · $LINEOR · <- 8C pin 6 B3 10 $LINEOR ↗ /$V1a · <- 9K pin 12 A4 12 /$V1a FLIP · <- 1/6 (same vertical that feeds pin 2) B4 13 FLIP OBFLIP2 · -> 6/6 Y1 3 OBFLIP2 drawn on b1-1-objram - click to jump there · $DMAPR · -> 6C pin 4 (~PR1): releases the bus request Y2 6 $DMAPR ↗ drawn on b1-2-objcontroller - click to jump there · $OBJLD · -> 7B pin 9, 7A pin 9, 10B pin 5 Y3 8 $OBJLD ↗ OBFLIP1 · -> 5/6 Y4 11 OBFLIP1 GND:7=GND VCC:14=+5V
· Original scan — manual p35 · zoom
original schematic scan
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