85605-B-1 Sheet 5/6 — LINE BUFFER 1

manual p36 · 15 ICs · 15 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Interboard connectors (the band cables between the boards) — circled letter+number labels on the drawing are connector row + pin
5L — 74LS163: X counter low: preloads DF0-DF3 (the sprite X byte) at /1LOAD, cleared per line at /1CL, counts at OB6M with P and T tied high so it free-runs; its carry (pin 15) enables 5M. — verified 2026-07-27 5L ✓ 74LS163 /1CL ~CL 1 /1CL OB6M CLK 2 OB6M DF0 A 3 DF0 DF1 B 4 DF1 DF2 C 5 DF2 DF3 D 6 DF3 +5V P 7 +5V /1LOAD ~LD 9 /1LOAD +5V T 10 +5V $X1D QD 11 $X1D $X1C QC 12 $X1C $X1B QB 13 $X1B $X1A QA 14 $X1A $X1CA1 · -> 5M pins 7 (P) and 10 (T) - ripple carry into the high counter CA 15 $X1CA1 GND:8=GND VCC:16=+5V 5M — 74LS163: X counter high: preloads DF4-DF7 at /1LOAD, cleared at /1CL, clocked at OB6M like 5L. Enabled by 5L's carry on pins 7/10, and passes its own carry on to 5K - so 5L/5M/5K form one 9-bit X counter across the sprite line. — verified 2026-07-27 5M ✓ 74LS163 /1CL ~CL 1 /1CL OB6M CLK 2 OB6M DF4 A 3 DF4 DF5 B 4 DF5 DF6 C 5 DF6 DF7 D 6 DF7 $X1CA1 · <- 5L pin 15 CA P 7 $X1CA1 /1LOAD ~LD 9 /1LOAD $X1CA1 · <- 5L pin 15 CA T 10 $X1CA1 $X1H QD 11 $X1H $X1G QC 12 $X1G $X1F QB 13 $X1F $X1E QA 14 $X1E $X1CA2 · -> 5K pins 7 (P) and 10 (T) - second stage of the ripple carry CA 15 $X1CA2 GND:8=GND VCC:16=+5V 5K — 74LS163: X counter bit 8: preloads HOVER (the sprite X msb from 3/6) with B/C/D grounded, enabled by 5M's carry. Its QA is the 9th X bit, and it drives /CE on both buffer RAMs - so as soon as the counter walks past 255 the RAM is deselected and the sprite is clipped at the right-hand edge of the line. QB/QC/QD and CA are unused. — verified 2026-07-27 5K ✓ 74LS163 /1CL ~CL 1 /1CL OB6M CLK 2 OB6M HOVER · from 3/6 A 3 HOVER GND B 4 GND GND C 5 GND GND D 6 GND $X1CA2 · <- 5M pin 15 CA P 7 $X1CA2 /1LOAD ~LD 9 /1LOAD $X1CA2 · <- 5M pin 15 CA T 10 $X1CA2 $X1OVER · -> 3K and 4K pin 8 /CE. Unlabelled on the sheet; $X1OVER is our name. | the sheet annotates this wire as bit 8 of the address bus QA 14 $X1OVER GND:8=GND VCC:16=+5V 4M — 74LS86: Flip XOR high. (A) inputs 1/4/9/12 take 5M's QA-QD; (Y) outputs 3/6/8/11 become RAM address A4-A7. Together with 4L it mirrors all eight X bits under OBFLIP1. — verified 2026-07-27 4M ✓ 74LS86 $X1E · <- 5M pin 14 A1 1 $X1E OBFLIP1 · the sheet letters this bundle just FLIP; it is OBFLIP1, in from 4/6 B1 2 OBFLIP1 $X1F · <- 5M pin 13 A2 4 $X1F OBFLIP1 · the sheet letters this bundle just FLIP; it is OBFLIP1, in from 4/6 B2 5 OBFLIP1 $X1G · <- 5M pin 12 A3 9 $X1G OBFLIP1 · the sheet letters this bundle just FLIP; it is OBFLIP1, in from 4/6 B3 10 OBFLIP1 $X1H · <- 5M pin 11 A4 12 $X1H OBFLIP1 · the sheet letters this bundle just FLIP; it is OBFLIP1, in from 4/6 B4 13 OBFLIP1 $BA4 · -> 3K/4K RAM address | the sheet annotates this address bus as bit indices 0-7, not by name Y1 3 $BA4 $BA5 · -> 3K/4K RAM address | the sheet annotates this address bus as bit indices 0-7, not by name Y2 6 $BA5 $BA6 · -> 3K/4K RAM address | the sheet annotates this address bus as bit indices 0-7, not by name Y3 8 $BA6 $BA7 · -> 3K/4K RAM address | the sheet annotates this address bus as bit indices 0-7, not by name Y4 11 $BA7 GND:7=GND VCC:14=+5V 4L — 74LS86: Flip XOR low. (A) inputs 1/4/9/12 take 5L's QA-QD; (Y) outputs 3/6/8/11 become RAM address A0-A3. OBFLIP1 on 2/5/10/13 inverts the four low X bits, so a horizontally flipped sprite walks its pixels into the line buffer backwards. — verified 2026-07-27 4L ✓ 74LS86 $X1A A1 1 $X1A OBFLIP1 · the sheet letters this bundle just FLIP; it is OBFLIP1, in from 4/6 B1 2 OBFLIP1 $X1B A2 4 $X1B OBFLIP1 · the sheet letters this bundle just FLIP; it is OBFLIP1, in from 4/6 B2 5 OBFLIP1 $X1C A3 9 $X1C OBFLIP1 · the sheet letters this bundle just FLIP; it is OBFLIP1, in from 4/6 B3 10 OBFLIP1 $X1D A4 12 $X1D OBFLIP1 · the sheet letters this bundle just FLIP; it is OBFLIP1, in from 4/6 B4 13 OBFLIP1 $BA0 · the repaired stuck-low output | the sheet annotates this address bus as bit indices 0-7, not by name Y1 3 $BA0 $BA1 · the sheet annotates this address bus as bit indices 0-7, not by name Y2 6 $BA1 $BA2 · the sheet annotates this address bus as bit indices 0-7, not by name Y3 8 $BA2 $BA3 · the sheet annotates this address bus as bit indices 0-7, not by name Y4 11 $BA3 GND:7=GND VCC:14=+5V 3K — 2148H: Line RAM low nibble, 1K x 4. Address A0-A7 comes from the flip XORs 4L/4M, A8/A9 grounded, so only 256 locations are used - one per pixel across the line. /CE is the 9th X bit, so the sprite clips at the right edge. Its data pins sit on a shared read-modify-write bus with 1K's '257: the RAM drives it while the mux is tri-stated, the mux samples it on (B), then drives the chosen value back during /1WR. RA4/RA5 (1K x 4) hold the bus when nobody drives it. — verified 2026-07-27 3K ✓ 2148H $BA6 · the sheet annotates this address bus as bit indices 0-7, not by name A6 1 $BA6 $BA5 · the sheet annotates this address bus as bit indices 0-7, not by name A5 2 $BA5 $BA4 · the sheet annotates this address bus as bit indices 0-7, not by name A4 3 $BA4 $BA3 · the sheet annotates this address bus as bit indices 0-7, not by name A3 4 $BA3 $BA0 · the sheet annotates this address bus as bit indices 0-7, not by name A0 5 $BA0 $BA1 · the sheet annotates this address bus as bit indices 0-7, not by name A1 6 $BA1 $BA2 · the sheet annotates this address bus as bit indices 0-7, not by name A2 7 $BA2 $X1OVER · <- 5K pin 14 QA - the 9th X bit deselects the RAM once the sprite runs off the line | the sheet annotates this wire as bit 8 of the address bus ~CE 8 $X1OVER /1WR · from 4/6 - one wire shared with 4K pin 10 ~WE 10 /1WR $BD3 · <-> 1K pin 4, pulled up to +5 through RA4 (1K x 4), read by 3L IO4 11 $BD3 $BD2 · <-> 1K pin 7, pulled up to +5 through RA4 (1K x 4), read by 3L IO3 12 $BD2 $BD1 · <-> 1K pin 9, pulled up to +5 through RA4 (1K x 4), read by 3L IO2 13 $BD1 $BD0 · <-> 1K pin 12, pulled up to +5 through RA4 (1K x 4), read by 3L IO1 14 $BD0 GND A9 15 GND GND A8 16 GND $BA7 · the sheet annotates this address bus as bit indices 0-7, not by name A7 17 $BA7 GND:9=GND VCC:18=+5V 4K — 2148H: Line RAM high nibble, 1K x 4. Shares everything with 3K - the same A0-A7 from the flip XORs, the same /CE from 5K's 9th X bit and the same /1WR on a single wire - so the pair behaves as one 256 x 8 line store, 3K holding the low nibble and 4K the high. Its data pins sit on the read-modify-write bus with 2K's '257. — verified 2026-07-27 4K ✓ 2148H $BA6 · the sheet annotates this address bus as bit indices 0-7, not by name A6 1 $BA6 $BA5 · the sheet annotates this address bus as bit indices 0-7, not by name A5 2 $BA5 $BA4 · the sheet annotates this address bus as bit indices 0-7, not by name A4 3 $BA4 $BA3 · the sheet annotates this address bus as bit indices 0-7, not by name A3 4 $BA3 $BA0 · the sheet annotates this address bus as bit indices 0-7, not by name A0 5 $BA0 $BA1 · the sheet annotates this address bus as bit indices 0-7, not by name A1 6 $BA1 $BA2 · the sheet annotates this address bus as bit indices 0-7, not by name A2 7 $BA2 $X1OVER · <- 5K pin 14 QA - the 9th X bit deselects the RAM once the sprite runs off the line | the sheet annotates this wire as bit 8 of the address bus ~CE 8 $X1OVER /1WR · from 4/6 - one wire shared with 3K pin 10 ~WE 10 /1WR $BD7 · <-> 2K pin 4, pulled up to +5 through RA5 (1K x 4), read by 3M IO4 11 $BD7 $BD6 · <-> 2K pin 7, pulled up to +5 through RA5 (1K x 4), read by 3M IO3 12 $BD6 $BD5 · <-> 2K pin 9, pulled up to +5 through RA5 (1K x 4), read by 3M IO2 13 $BD5 $BD4 · <-> 2K pin 12, pulled up to +5 through RA5 (1K x 4), read by 3M IO1 14 $BD4 GND A9 15 GND GND A8 16 GND $BA7 · the sheet annotates this address bus as bit indices 0-7, not by name A7 17 $BA7 GND:9=GND VCC:18=+5V 1L — 74LS20: Transparency test / first-sprite priority. NANDs the low nibble read back from the RAM: all four bits high means pen 15, i.e. nothing has been written to that pixel yet, so the output drops and steers both write-back muxes to take the new sprite pixel. Any other value means an earlier sprite already owns the pixel and it is written straight back unchanged - so the first sprite to reach a pixel keeps it. Only one of the '20's two gates is drawn on this sheet. — verified 2026-07-27 1L ✓ 74LS20 OB10 A 1 OB10 OB13 D 2 OB13 OB11 B 4 OB11 OB12 C 5 OB12 drawn on b1-6-linebuffer2 - click to jump there · OB21 · <- 10L B 9 OB21 ↗ drawn on b1-6-linebuffer2 - click to jump there · OB22 · <- 10L C 10 OB22 ↗ drawn on b1-6-linebuffer2 - click to jump there · OB20 · <- 10L A 12 OB20 ↗ drawn on b1-6-linebuffer2 - click to jump there · OB23 · <- 10L D 13 OB23 ↗ /$B1EMPTY · one wire to SEL on both 1K pin 1 and 2K pin 1 Y 6 /$B1EMPTY drawn on b1-6-linebuffer2 - click to jump there · /$B2EMPTY · one wire to SEL on both 8L and 8M Y 8 /$B2EMPTY ↗ GND:7=GND VCC:14=+5V 1K — 74LS257: Write-back mux, low nibble. (A) = COL0-COL3, the incoming sprite pixel; (B) = OB10-OB13, the value 3L latched out of the RAM; (Y) drives the RAM data bus. 1L's transparency test picks between them, so a pixel is only overwritten while the slot still reads as empty - first sprite wins. Tri-stated by /1ST so the RAM can drive the same bus during the read half. — verified 2026-07-27 1K ✓ 74LS257 /$B1EMPTY · <- 1L pin 6, shared SEL 1 /$B1EMPTY COL3 · from 4/6 4A 2 COL3 OB13 4B 3 OB13 COL2 · from 4/6 3A 5 COL2 OB12 3B 6 OB12 OB11 2B 10 OB11 COL1 · from 4/6 2A 11 COL1 OB10 1B 13 OB10 COL0 · from 4/6 1A 14 COL0 /1ST · from 4/6 - one line to both muxes ~ST 15 /1ST $BD3 · -> 3K pin 11 (shared bus, RA4 pull-up) 4Y 4 $BD3 $BD2 · -> 3K pin 12 (shared bus, RA4 pull-up) 3Y 7 $BD2 $BD1 · -> 3K pin 13 (shared bus, RA4 pull-up) 2Y 9 $BD1 $BD0 · -> 3K pin 14 (shared bus, RA4 pull-up) 1Y 12 $BD0 GND:8=GND VCC:16=+5V 2K — 74LS257: Write-back mux, high nibble. A sprite pixel is only six bits, so only (A) inputs 14 and 11 are used - COL4 and COL5 in from 3/6. Inputs 5 and 2 are left genuinely open (no trace on the board), so the buffer's top two bits are whatever the RA5 pull-ups give when a sprite writes. (B) takes OB14-OB17 back from 3M, (Y) drives the 4K data bus, and SEL and /1ST are shared with 1K so both nibbles switch together. — verified 2026-07-27 2K ✓ 74LS257 /$B1EMPTY · <- 1L pin 6, shared SEL 1 /$B1EMPTY OB17 4B 3 OB17 OB16 3B 6 OB16 OB15 2B 10 OB15 COL5 · from 3/6 2A 11 COL5 OB14 1B 13 OB14 COL4 · from 3/6 1A 14 COL4 /1ST · from 4/6 - one line to both muxes ~ST 15 /1ST $BD7 · -> 4K pin 11 (shared bus, RA5 pull-up) 4Y 4 $BD7 $BD6 · -> 4K pin 12 (shared bus, RA5 pull-up) 3Y 7 $BD6 $BD5 · -> 4K pin 13 (shared bus, RA5 pull-up) 2Y 9 $BD5 $BD4 · -> 4K pin 14 (shared bus, RA5 pull-up) 1Y 12 $BD4 GND:8=GND VCC:16=+5V 3L — 74LS174: Playback latch, low nibble. Registers the RAM data bus at L6MB and presents it as OB10-OB13 - the value the screen sees, the value 1K compares against on its (B) side, and (for 3L) the value 1L tests for transparency. Cleared each line by /1CL so stale pixels cannot leak through. Only four of the '174's six flip-flops are used. — verified 2026-07-27 3L ✓ 74LS174 /1CL · from 4/6 - cleared at the start of every line (corrected 2026-07-27; was recorded as +5) ~CL 1 /1CL $BD3 · <- shared RAM data bus (3K D pins / 1K (Y)) D1 3 $BD3 $BD2 · <- shared RAM data bus (3K D pins / 1K (Y)) D2 4 $BD2 $BD1 · <- shared RAM data bus (3K D pins / 1K (Y)) D3 6 $BD1 L6MB · from 4/6 - the buffered 6M pixel clock CLK 9 L6MB $BD0 · <- shared RAM data bus (3K D pins / 1K (Y)) D4 11 $BD0 OB13 Q1 2 OB13 OB12 Q2 5 OB12 OB11 Q3 7 OB11 OB10 Q4 10 OB10 GND:8=GND VCC:16=+5V 3M — 74LS174: Playback latch, high nibble. Registers the RAM data bus at L6MB and presents it as OB14-OB17 - the value the screen sees, the value 2K compares against on its (B) side, and (for 3L) the value 1L tests for transparency. Cleared each line by /1CL so stale pixels cannot leak through. Only four of the '174's six flip-flops are used. — verified 2026-07-27 3M ✓ 74LS174 /1CL · from 4/6 - cleared at the start of every line (corrected 2026-07-27; was recorded as +5) ~CL 1 /1CL $BD7 · <- shared RAM data bus (4K D pins / 2K (Y)) D1 3 $BD7 $BD6 · <- shared RAM data bus (4K D pins / 2K (Y)) D2 4 $BD6 $BD5 · <- shared RAM data bus (4K D pins / 2K (Y)) D3 6 $BD5 L6MB · from 4/6 - the buffered 6M pixel clock CLK 9 L6MB $BD4 · <- shared RAM data bus (4K D pins / 2K (Y)) D4 11 $BD4 OB17 Q1 2 OB17 OB16 Q2 5 OB16 OB15 Q3 7 OB15 OB14 Q4 10 OB14 GND:8=GND VCC:16=+5V 2L — 74LS257: Buffer output mux, low nibble. (A) takes this sheet's own buffer from 3L, (B) takes the other buffer's from 6/6, and V1a on SEL flips between them every line - so one buffer is being played out to the screen while the other is being filled with the next line's sprites. /DISPTMa blanks the output outside the display window. Drives OBJ0-OBJ3 into 1M. Note the sheet numbers the mux channels 1-4 top to bottom, opposite to the datasheet. — verified 2026-07-27 2L ✓ 74LS257 V1a · from 4/6 - one line to both 2L and 2M SEL 1 V1a OB13 · <- 3L (this buffer) 4A 2 OB13 OB23 · <- 6/6 (the other line buffer) 4B 3 OB23 OB12 · <- 3L (this buffer) 3A 5 OB12 OB22 · <- 6/6 (the other line buffer) 3B 6 OB22 OB21 · <- 6/6 (the other line buffer) 2B 10 OB21 OB11 · <- 3L (this buffer) 2A 11 OB11 OB20 · <- 6/6 (the other line buffer) 1B 13 OB20 OB10 · <- 3L (this buffer) 1A 14 OB10 /DISPTMa · from 4/6 - one line to both 2L and 2M ~ST 15 /DISPTMa OBJ3 · -> 1M 4Y 4 OBJ3 OBJ2 · -> 1M 3Y 7 OBJ2 OBJ1 · -> 1M 2Y 9 OBJ1 OBJ0 · -> 1M 1Y 12 OBJ0 GND:8=GND VCC:16=+5V 2M — 74LS257: Buffer output mux, high nibble. (A) takes this sheet's own buffer from 3M, (B) takes the other buffer's from 6/6, and V1a on SEL flips between them every line - so one buffer is being played out to the screen while the other is being filled with the next line's sprites. /DISPTMa blanks the output outside the display window. Drives OBJ4-OBJ7 into 1M. Note the sheet numbers the mux channels 1-4 top to bottom, opposite to the datasheet. — verified 2026-07-27 2M ✓ 74LS257 V1a · from 4/6 - one line to both 2L and 2M SEL 1 V1a OB17 · <- 3M (this buffer) 4A 2 OB17 OB27 · <- 6/6 (the other line buffer) 4B 3 OB27 OB16 · <- 3M (this buffer) 3A 5 OB16 OB26 · <- 6/6 (the other line buffer) 3B 6 OB26 OB25 · <- 6/6 (the other line buffer) 2B 10 OB25 OB15 · <- 3M (this buffer) 2A 11 OB15 OB24 · <- 6/6 (the other line buffer) 1B 13 OB24 OB14 · <- 3M (this buffer) 1A 14 OB14 /DISPTMa · from 4/6 - one line to both 2L and 2M ~ST 15 /DISPTMa OBJ7 · -> 1M 4Y 4 OBJ7 OBJ6 · -> 1M 3Y 7 OBJ6 OBJ5 · -> 1M 2Y 9 OBJ5 OBJ4 · -> 1M 1Y 12 OBJ4 GND:8=GND VCC:16=+5V 1M — 74LS273: Final sprite output register, clocked at OB6M. Takes the eight bits the buffer muxes selected and presents them to the A board on CN-2 as OBJA-OBJH. Only OBJA-OBJF carry real data - a sprite pixel is six bits - and nothing on the A board reads OBJG or OBJH, which is why 2K's two spare mux inputs could be left open. Clear is tied high. — verified 2026-07-27 1M ✓ 74LS273 +5V · clear tied high ~CL 1 +5V OBJ0 · <- 2L/2M D1 3 OBJ0 OBJ1 · <- 2L/2M D2 4 OBJ1 OBJ2 · <- 2L/2M D3 7 OBJ2 OBJ3 · <- 2L/2M D4 8 OBJ3 OB6M · from 4/6 CLK 11 OB6M OBJ4 · <- 2L/2M D5 13 OBJ4 OBJ5 · <- 2L/2M D6 14 OBJ5 OBJ6 · <- 2L/2M D7 17 OBJ6 OBJ7 · <- 2L/2M D8 18 OBJ7 OBJA · -> CN-2 D17 Q1 2 OBJA OBJB · -> CN-2 C17 Q2 5 OBJB OBJC · -> CN-2 D16 Q3 6 OBJC OBJD · -> CN-2 C16 Q4 9 OBJD OBJE · -> CN-2 D15 Q5 12 OBJE OBJF · -> CN-2 C15 Q6 15 OBJF OBJG · -> CN-2 D14. EXPLAINED, not a gap: the cable carries 8 sprite bits (manual p11 lists both pins) but a Commando sprite pixel is only 6 (4 colour + 2 palette), so nothing on the A board reads this line. Same two bits are the unconnected mux inputs on 2K/8M. Q7 16 OBJG OBJH · -> CN-2 C14. EXPLAINED, not a gap: the cable carries 8 sprite bits (manual p11 lists both pins) but a Commando sprite pixel is only 6 (4 colour + 2 palette), so nothing on the A board reads this line. Same two bits are the unconnected mux inputs on 2K/8M. Q8 19 OBJH GND:10=GND VCC:20=+5V
· Original scan — manual p36 · zoom
original schematic scan
5L
5M
5K
4M
4L
3K
4K
1L
1K
2K
3L
3M
2L
2M
1M