85605-B-1 Sheet 6/6 — LINE BUFFER 2

manual p37 · 12 ICs · 12 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
6L — 74LS163: X counter low for buffer 2 - the mirror of 5L on sheet 5/6. Preloads DF0-DF3 at /2LOAD, cleared per line at /2CL, counts at OB6M with P and T tied high, and carries into 6M. — verified 2026-07-27 6L ✓ 74LS163 /2CL · from 4/6 ~CL 1 /2CL OB6M · from 4/6 CLK 2 OB6M DF0 · from 3/6 A 3 DF0 DF1 · from 3/6 B 4 DF1 DF2 · from 3/6 C 5 DF2 DF3 · from 3/6 D 6 DF3 +5V P 7 +5V /2LOAD · from 4/6 ~LD 9 /2LOAD +5V T 10 +5V $X2D · -> 7L QD 11 $X2D $X2C · -> 7L QC 12 $X2C $X2B · -> 7L QB 13 $X2B $X2A · -> 7L QA 14 $X2A $X2CA1 · -> 6M pins 7 (P) and 10 (T) - ripple carry into the high counter CA 15 $X2CA1 GND:8=GND VCC:16=+5V 6M — 74LS163: X counter high for buffer 2 - the mirror of 5M. Preloads DF4-DF7 at /2LOAD, enabled by 6L's carry, and carries on into 6K, so 6L/6M/6K make one 9-bit X counter as on sheet 5/6. — verified 2026-07-27 6M ✓ 74LS163 /2CL · from 4/6 ~CL 1 /2CL OB6M · from 4/6 CLK 2 OB6M DF4 · from 3/6 A 3 DF4 DF5 · from 3/6 B 4 DF5 DF6 · from 3/6 C 5 DF6 DF7 · from 3/6 D 6 DF7 $X2CA1 · <- 6L pin 15 CA P 7 $X2CA1 /2LOAD · from 4/6 ~LD 9 /2LOAD $X2CA1 · <- 6L pin 15 CA T 10 $X2CA1 $X2H · -> 7M QD 11 $X2H $X2G · -> 7M QC 12 $X2G $X2F · -> 7M QB 13 $X2F $X2E · -> 7M QA 14 $X2E $X2CA2 · -> 6K pins 7 (P) and 10 (T) CA 15 $X2CA2 GND:8=GND VCC:16=+5V 6K — 74LS163: X counter bit 8 for buffer 2 - the mirror of 5K. Preloads HOVER with B/C/D grounded, enabled by 6M's carry. Its QA is address bit 8 of the line RAM, and because the RAM is only 256 deep that bit is wired to /CE: the moment the X counter passes pixel 255 the RAM deselects and the sprite clips at the right edge. QB/QC/QD and CA unused. — verified 2026-07-27 6K ✓ 74LS163 /2CL · from 4/6 ~CL 1 /2CL OB6M · from 4/6 CLK 2 OB6M HOVER · from 3/6 A 3 HOVER GND · strapped together to ground B 4 GND GND · strapped together to ground C 5 GND GND · strapped together to ground D 6 GND $X2CA2 · <- 6M pin 15 CA P 7 $X2CA2 /2LOAD · from 4/6 ~LD 9 /2LOAD $X2CA2 · <- 6M pin 15 CA T 10 $X2CA2 $X2OVER · -> 9L and 9M pin 8 /CE - address bit 8, drawn as line '8' on the bus | the sheet annotates this wire as bit 8 of the address bus QA 14 $X2OVER GND:8=GND VCC:16=+5V 7L — 74LS86: Flip XOR for buffer 2 (low half) - the mirror of 4L on sheet 5/6. OBFLIP2 inverts the X bits so a horizontally flipped sprite writes its pixels into the line backwards. — verified 2026-07-27 7L ✓ 74LS86 $X2A · <- 6L pin 14 A1 1 $X2A OBFLIP2 · the sheet letters this bundle just FLIP; it is OBFLIP2, in from 4/6 B1 2 OBFLIP2 $X2B · <- 6L pin 13 A2 4 $X2B OBFLIP2 · the sheet letters this bundle just FLIP; it is OBFLIP2, in from 4/6 B2 5 OBFLIP2 $X2C · <- 6L pin 12 A3 9 $X2C OBFLIP2 · the sheet letters this bundle just FLIP; it is OBFLIP2, in from 4/6 B3 10 OBFLIP2 $X2D · <- 6L pin 11 A4 12 $X2D OBFLIP2 · the sheet letters this bundle just FLIP; it is OBFLIP2, in from 4/6 B4 13 OBFLIP2 $LB2CA0 · -> 9L/9M RAM address | the sheet annotates this address bus as bit indices 0-7, not by name Y1 3 $LB2CA0 $LB2CA1 · -> 9L/9M RAM address | the sheet annotates this address bus as bit indices 0-7, not by name Y2 6 $LB2CA1 $LB2CA2 · -> 9L/9M RAM address | the sheet annotates this address bus as bit indices 0-7, not by name Y3 8 $LB2CA2 $LB2CA3 · -> 9L/9M RAM address | the sheet annotates this address bus as bit indices 0-7, not by name Y4 11 $LB2CA3 GND:7=GND VCC:14=+5V 7M — 74LS86: Flip XOR for buffer 2 (high half) - the mirror of 4M on sheet 5/6. OBFLIP2 inverts the X bits so a horizontally flipped sprite writes its pixels into the line backwards. — verified 2026-07-27 7M ✓ 74LS86 $X2E · <- 6M pin 14 A1 1 $X2E OBFLIP2 · the sheet letters this bundle just FLIP; it is OBFLIP2, in from 4/6 B1 2 OBFLIP2 $X2F · <- 6M pin 13 A2 4 $X2F OBFLIP2 · the sheet letters this bundle just FLIP; it is OBFLIP2, in from 4/6 B2 5 OBFLIP2 $X2G · <- 6M pin 12 A3 9 $X2G OBFLIP2 · the sheet letters this bundle just FLIP; it is OBFLIP2, in from 4/6 B3 10 OBFLIP2 $X2H · <- 6M pin 11 A4 12 $X2H OBFLIP2 · the sheet letters this bundle just FLIP; it is OBFLIP2, in from 4/6 B4 13 OBFLIP2 $LB2CA4 · -> 9L/9M RAM address | the sheet annotates this address bus as bit indices 0-7, not by name Y1 3 $LB2CA4 $LB2CA5 · -> 9L/9M RAM address | the sheet annotates this address bus as bit indices 0-7, not by name Y2 6 $LB2CA5 $LB2CA6 · -> 9L/9M RAM address | the sheet annotates this address bus as bit indices 0-7, not by name Y3 8 $LB2CA6 $LB2CA7 · -> 9L/9M RAM address | the sheet annotates this address bus as bit indices 0-7, not by name Y4 11 $LB2CA7 GND:7=GND VCC:14=+5V 9L — 2148H: Line RAM for buffer 2, low nibble - the mirror of 3K on sheet 5/6. A0-A7 from the flip XORs, A8/A9 grounded, /CE is the 9th X bit so the sprite clips at the right edge, /2WR shared with its partner. Data pins sit on the read-modify-write bus with 8L's '257 and are read by 10L. — verified 2026-07-27 9L ✓ 2148H $LB2CA6 · the sheet annotates this address bus as bit indices 0-7, not by name A6 1 $LB2CA6 $LB2CA5 · the sheet annotates this address bus as bit indices 0-7, not by name A5 2 $LB2CA5 $LB2CA4 · the sheet annotates this address bus as bit indices 0-7, not by name A4 3 $LB2CA4 $LB2CA3 · the sheet annotates this address bus as bit indices 0-7, not by name A3 4 $LB2CA3 $LB2CA0 · the sheet annotates this address bus as bit indices 0-7, not by name A0 5 $LB2CA0 $LB2CA1 · the sheet annotates this address bus as bit indices 0-7, not by name A1 6 $LB2CA1 $LB2CA2 · the sheet annotates this address bus as bit indices 0-7, not by name A2 7 $LB2CA2 $X2OVER · <- 6K pin 14 QA - the 9th address bit doubles as chip enable, clipping the sprite at the right edge of the line | the sheet annotates this wire as bit 8 of the address bus ~CE 8 $X2OVER /2WR · from 4/6 - one wire shared with the other RAM ~WE 10 /2WR $CD3 · <-> 8L pin 4 through the RA6 pull-ups, read by 10L IO4 11 $CD3 $CD2 · <-> 8L pin 7 through the RA6 pull-ups, read by 10L IO3 12 $CD2 $CD1 · <-> 8L pin 9 through the RA6 pull-ups, read by 10L IO2 13 $CD1 $CD0 · <-> 8L pin 12 through the RA6 pull-ups, read by 10L IO1 14 $CD0 GND A9 15 GND GND A8 16 GND $LB2CA7 · the sheet annotates this address bus as bit indices 0-7, not by name A7 17 $LB2CA7 GND:9=GND VCC:18=+5V 9M — 2148H: Line RAM for buffer 2, high nibble - the mirror of 4K on sheet 5/6. A0-A7 from the flip XORs, A8/A9 grounded, /CE is the 9th X bit so the sprite clips at the right edge, /2WR shared with its partner. Data pins sit on the read-modify-write bus with 8M's '257 and are read by 10M. — verified 2026-07-27 9M ✓ 2148H $LB2CA6 · the sheet annotates this address bus as bit indices 0-7, not by name A6 1 $LB2CA6 $LB2CA5 · the sheet annotates this address bus as bit indices 0-7, not by name A5 2 $LB2CA5 $LB2CA4 · the sheet annotates this address bus as bit indices 0-7, not by name A4 3 $LB2CA4 $LB2CA3 · the sheet annotates this address bus as bit indices 0-7, not by name A3 4 $LB2CA3 $LB2CA0 · the sheet annotates this address bus as bit indices 0-7, not by name A0 5 $LB2CA0 $LB2CA1 · the sheet annotates this address bus as bit indices 0-7, not by name A1 6 $LB2CA1 $LB2CA2 · the sheet annotates this address bus as bit indices 0-7, not by name A2 7 $LB2CA2 $X2OVER · <- 6K pin 14 QA - the 9th address bit doubles as chip enable, clipping the sprite at the right edge of the line | the sheet annotates this wire as bit 8 of the address bus ~CE 8 $X2OVER /2WR · from 4/6 - one wire shared with the other RAM ~WE 10 /2WR $CD7 · <-> 8M pin 4 through the RA7 pull-ups, read by 10M IO4 11 $CD7 $CD6 · <-> 8M pin 7 through the RA7 pull-ups, read by 10M IO3 12 $CD6 $CD5 · <-> 8M pin 9 through the RA7 pull-ups, read by 10M IO2 13 $CD5 $CD4 · <-> 8M pin 12 through the RA7 pull-ups, read by 10M IO1 14 $CD4 GND A9 15 GND GND A8 16 GND $LB2CA7 · the sheet annotates this address bus as bit indices 0-7, not by name A7 17 $LB2CA7 GND:9=GND VCC:18=+5V 1L — 74LS20: Transparency test for buffer 2 - gate 2 of the same physical '20 whose gate 1 serves buffer 1 on sheet 5/6. NANDs the low nibble read back from the RAM: all four bits high means pen 15, the pixel is still empty, so the output drops and steers both write-back muxes to take the new sprite pixel. One chip, one gate per line buffer. — verified 2026-07-27 1L ✓ 74LS20 drawn on b1-5-linebuffer1 - click to jump there · OB10 A 1 OB10 ↗ drawn on b1-5-linebuffer1 - click to jump there · OB13 D 2 OB13 ↗ drawn on b1-5-linebuffer1 - click to jump there · OB11 B 4 OB11 ↗ drawn on b1-5-linebuffer1 - click to jump there · OB12 C 5 OB12 ↗ OB21 · <- 10L B 9 OB21 OB22 · <- 10L C 10 OB22 OB20 · <- 10L A 12 OB20 OB23 · <- 10L D 13 OB23 drawn on b1-5-linebuffer1 - click to jump there · /$B1EMPTY · one wire to SEL on both 1K pin 1 and 2K pin 1 Y 6 /$B1EMPTY ↗ /$B2EMPTY · one wire to SEL on both 8L and 8M Y 8 /$B2EMPTY GND:7=GND VCC:14=+5V 8L — 74LS257: Write-back mux for buffer 2, low nibble - the mirror of 1K on sheet 5/6. (A) is the incoming sprite pixel, (B) is the value 10L latched back out of the RAM, and 1L's transparency test picks between them so the first sprite to reach a pixel keeps it. Tri-stated by /2ST while the RAM drives the shared bus. Note the sheet numbers the mux channels 1-4 top to bottom, opposite to the datasheet. — verified 2026-07-27 8L ✓ 74LS257 /$B2EMPTY · <- 1L pin 8, shared with the other mux SEL 1 /$B2EMPTY COL3 · from 4/6 4A 2 COL3 OB23 · <- 10L 4B 3 OB23 COL2 · from 4/6 3A 5 COL2 OB22 · <- 10L 3B 6 OB22 OB21 · <- 10L 2B 10 OB21 COL1 · from 4/6 2A 11 COL1 OB20 · <- 10L 1B 13 OB20 COL0 · from 4/6 1A 14 COL0 /2ST · from 4/6 - one line to both muxes ~ST 15 /2ST $CD3 · -> 9L pin 11 and 10L pin 3 (shared bus) 4Y 4 $CD3 $CD2 · -> 9L pin 12 and 10L pin 4 (shared bus) 3Y 7 $CD2 $CD1 · -> 9L pin 13 and 10L pin 6 (shared bus) 2Y 9 $CD1 $CD0 · -> 9L pin 14 and 10L pin 11 (shared bus) 1Y 12 $CD0 GND:8=GND VCC:16=+5V 8M — 74LS257: Write-back mux for buffer 2, high nibble - the mirror of 2K on sheet 5/6. (A) is the incoming sprite pixel, (B) is the value 10M latched back out of the RAM, and 1L's transparency test picks between them so the first sprite to reach a pixel keeps it. Tri-stated by /2ST while the RAM drives the shared bus. Note the sheet numbers the mux channels 1-4 top to bottom, opposite to the datasheet. — verified 2026-07-27 8M ✓ 74LS257 /$B2EMPTY · <- 1L pin 8, shared with the other mux SEL 1 /$B2EMPTY OB27 · <- 10M 4B 3 OB27 OB26 · <- 10M 3B 6 OB26 OB25 · <- 10M 2B 10 OB25 COL5 · from 3/6 2A 11 COL5 OB24 · <- 10M 1B 13 OB24 COL4 · from 3/6 1A 14 COL4 /2ST · from 4/6 - one line to both muxes ~ST 15 /2ST $CD7 · -> 9M pin 11 and 10M pin 3 (shared bus) 4Y 4 $CD7 $CD6 · -> 9M pin 12 and 10M pin 4 (shared bus) 3Y 7 $CD6 $CD5 · -> 9M pin 13 and 10M pin 6 (shared bus) 2Y 9 $CD5 $CD4 · -> 9M pin 14 and 10M pin 11 (shared bus) 1Y 12 $CD4 GND:8=GND VCC:16=+5V 10L — 74LS174: Playback latch for buffer 2, low nibble - the mirror of 3L. Registers the RAM data bus at L6MB and sends it across to sheet 5/6, where it arrives on the (B) side of the output muxes. Cleared each line by /2CL so stale pixels cannot leak through. Two of the '174's six flip-flops are unused. — verified 2026-07-27 10L ✓ 74LS174 /2CL · from 4/6 - cleared at the start of every line ~CL 1 /2CL $CD3 · <- shared RAM data bus D1 3 $CD3 $CD2 · <- shared RAM data bus D2 4 $CD2 $CD1 · <- shared RAM data bus D3 6 $CD1 L6MB · from 4/6 - the buffered 6M pixel clock CLK 9 L6MB $CD0 · <- shared RAM data bus D4 11 $CD0 OB23 · -> 5/6 (2L/2M (B) side) Q1 2 OB23 OB22 · -> 5/6 (2L/2M (B) side) Q2 5 OB22 OB21 · -> 5/6 (2L/2M (B) side) Q3 7 OB21 OB20 · -> 5/6 (2L/2M (B) side) Q4 10 OB20 GND:8=GND VCC:16=+5V 10M — 74LS174: Playback latch for buffer 2, high nibble - the mirror of 3M. Registers the RAM data bus at L6MB and sends it across to sheet 5/6, where it arrives on the (B) side of the output muxes. Cleared each line by /2CL so stale pixels cannot leak through. Two of the '174's six flip-flops are unused. — verified 2026-07-27 10M ✓ 74LS174 /2CL · from 4/6 - cleared at the start of every line ~CL 1 /2CL $CD7 · <- shared RAM data bus D1 3 $CD7 $CD6 · <- shared RAM data bus D2 4 $CD6 $CD5 · <- shared RAM data bus D3 6 $CD5 L6MB · from 4/6 - the buffered 6M pixel clock CLK 9 L6MB $CD4 · <- shared RAM data bus D4 11 $CD4 OB27 · -> 5/6 (2L/2M (B) side) Q1 2 OB27 OB26 · -> 5/6 (2L/2M (B) side) Q2 5 OB26 OB25 · -> 5/6 (2L/2M (B) side) Q3 7 OB25 OB24 · -> 5/6 (2L/2M (B) side) Q4 10 OB24 GND:8=GND VCC:16=+5V
· Original scan — manual p37 · zoom
original schematic scan
6L
6M
6K
7L
7M
9L
9M
1L
8L
8M
10L
10M