85605-C-1 Sheet 1/3 — SCROLL H POSITION

manual p20 · 16 ICs · 16 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Interboard connectors (the band cables between the boards) — circled letter+number labels on the drawing are connector row + pin
2A — 74LS138: Scroll register write decode: C808-C80B -> POS0-POS3 (X low / X hi / Y low / Y hi) — verified 2026-07-21 2A ✓ 74LS138 AB0 · buffered CPU address (feeds through to 2/3) · from CN-1 A13 A 1 AB0 AB1 · buffered CPU address · from CN-1 A14 B 2 AB1 AB2 · buffered CPU address · from CN-1 A15 C 3 AB2 /C8CS · C800 block write select from the A board, active low · from CN-1 B13 ~G2A 4 /C8CS /C8CS · C800 block write select from the A board, active low · from CN-1 B13 ~G2B 5 /C8CS AB3 · buffered CPU address · from CN-1 A16 G1 6 AB3 POS3 · C80B write strobe - scroll Y bit 8 (6C unit 1) · to sheet 2/3 Y3 12 POS3 POS2 · C80A write strobe - scroll Y low (5C) · to sheet 2/3 Y2 13 POS2 POS1 · C809 write strobe - scroll X bit 8 (6C) Y1 14 POS1 POS0 · C808 write strobe - scroll X low (4C) Y0 15 POS0 GND:8=GND VCC:16=+5V 9C — 74LS04: Unit on this sheet: /DBCS (CN-1 B14) inverter (in 5, out 6) -> DBCS to the 9D grant flip-flop's /CL — verified 2026-07-21 9C ✓ 74LS04 drawn on c1-3-scrollrom - click to jump there · /S7H · sub-tile phase 7 strobe (7D Y7) - shifter load on 3/3, also 8D D2 and the grant clock · to sheet 3/3 A1 1 /S7H ↗ drawn on c1-3-scrollrom - click to jump there · AS9 A2 3 AS9 ↗ /D8CS · renamed 2026-07-27: same net as io 3B pin 7 /$D8CS (D800-DFFF, CN-1 B14) - was an 8 vs B split A3 5 /D8CS drawn on c1-3-scrollrom - click to jump there · $FSFLIP A6 13 $FSFLIP ↗ drawn on c1-3-scrollrom - click to jump there · $S7H Y1 2 $S7H ↗ drawn on c1-3-scrollrom - click to jump there · /$AS9 Y2 4 /$AS9 ↗ $D8CS · renamed 2026-07-27: same net as io 3B pin 7 /$D8CS (D800-DFFF, CN-1 B14) - was an 8 vs B split Y3 6 $D8CS drawn on c1-3-scrollrom - click to jump there · /$FSFLIP Y6 12 /$FSFLIP ↗ GND:7=GND VCC:14=+5V 9D — 74LS74: Unit 1: VRAM access grant - D=+5, set on an S4H edge, async-cleared by DBCS (9C pin 6) when the CPU leaves D800-DFFF; Q=SCREN //Q=LSCREN to 2/3. Unit 2: phiSC generator (D=+5, set on /H1 edge, async-cleared by the 8E gate) -> A board B15 — verified 2026-07-21 9D ✓ 74LS74 $D8CS · renamed 2026-07-27: same net as io 3B pin 7 /$D8CS (D800-DFFF, CN-1 B14) - was an 8 vs B split ~CL1 1 $D8CS +5V D1 2 +5V S4H · latched fetch strobe (8D /Q3) - clocks the 3A attr latch on 2/3 and the 9D grant flip-flop · to sheet 2/3 CLK1 3 S4H +5V ~PR1 4 +5V +5V ~PR2 10 +5V /H1 · inverted H1 (9E) - clock for the phiSC divider CLK2 11 /H1 +5V D2 12 +5V $PHISCCL ~CL2 13 $PHISCCL SCREN · CPU VRAM access grant (9D Q) - high = CPU may access · to sheet 2/3 Q1 5 SCREN LSCREN · inverted grant (9D /Q), active low: selects CPU address + enables 3C on 2/3 · to sheet 2/3 ~Q1 6 LSCREN PHISC · phiSC to the A board - 9D FF with D=+5: set on an /H1 edge, async-cleared by the 8E gate (a synchronized pulse, not a divided clock) · to CN-1 B15 Q2 9 PHISC GND:7=GND VCC:14=+5V 4C — 74LS273: Scroll X register low byte - CPU write C808 (POS0). Same reversed bit order as 5C on 2/3 — verified 2026-07-21 4C ✓ 74LS273 +5V ~CL 1 +5V DB7 · buffered CPU data bus · from CN-1 A8 D1 3 DB7 DB6 · buffered CPU data bus · from CN-1 A7 D2 4 DB6 DB5 · buffered CPU data bus · from CN-1 A6 D3 7 DB5 DB4 · buffered CPU data bus · from CN-1 A5 D4 8 DB4 POS0 · C808 write strobe - scroll X low (4C) CLK 11 POS0 DB3 · buffered CPU data bus · from CN-1 A4 D5 13 DB3 DB2 · buffered CPU data bus · from CN-1 A3 D6 14 DB2 DB1 · buffered CPU data bus · from CN-1 A2 D7 17 DB1 DB0 · buffered CPU data bus (feeds through to 2/3) · from CN-1 A1 D8 18 DB0 $SCX7 Q1 2 $SCX7 $SCX6 Q2 5 $SCX6 $SCX5 Q3 6 $SCX5 $SCX4 Q4 9 $SCX4 $SCX3 Q5 12 $SCX3 $SCX2 Q6 15 $SCX2 $SCX1 Q7 16 $SCX1 $SCX0 Q8 19 $SCX0 GND:10=GND VCC:20=+5V 6C — 74LS74: Unit on this sheet: scroll X bit 8 - CPU write C809 (POS1, 2A Y1) latches DB0 -> 5D adder — verified 2026-07-21 6C ✓ 74LS74 drawn on c1-2-scrollvram - click to jump there · +5V ~CL 1 +5V ↗ drawn on c1-2-scrollvram - click to jump there · DB0 · buffered CPU data bus (feeds through to 2/3) · from CN-1 A1 D 2 DB0 ↗ drawn on c1-2-scrollvram - click to jump there · POS3 · C80B write strobe - scroll Y bit 8 (6C unit 1) · to sheet 2/3 CLK 3 POS3 ↗ drawn on c1-2-scrollvram - click to jump there · +5V ~PR 4 +5V ↗ +5V ~PR 10 +5V POS1 · C809 write strobe - scroll X bit 8 (6C) CLK 11 POS1 DB0 · buffered CPU data bus (feeds through to 2/3) · from CN-1 A1 D 12 DB0 +5V ~CL 13 +5V drawn on c1-2-scrollvram - click to jump there · $SCY8 Q 5 $SCY8 ↗ $SCX8 Q 9 $SCX8 GND:7=GND VCC:14=+5V 2D — 74LS86: H16-H128 XOR FLIP (screen flip on H counter, high bits). Gate order scrambled (g4=H128, g1=H64, g2=H32, g3=H16) - walkthrough-verified — verified 2026-07-21 2D ✓ 74LS86 H64 · H counter bit · from CN-2 C8 A1 1 H64 $CFLIPb B1 2 $CFLIPb H32 · H counter bit · from CN-2 D7 A2 4 H32 $CFLIPb B2 5 $CFLIPb H16 · H counter bit · from CN-2 C7 A3 9 H16 $CFLIPb B3 10 $CFLIPb H128 · H counter bit · from CN-2 D8 A4 12 H128 $CFLIPb B4 13 $CFLIPb H64F · flip-XORed H bit (2D) -> 4D B3 + the 7E correction XOR Y1 3 H64F H32F · flip-XORed H bit (2D) Y2 6 H32F H16F · flip-XORed H bit (2D) Y3 8 H16F H128F · flip-XORed H bit (2D) -> only into the 7E correction XOR (4D B4 gets the corrected H128C) Y4 11 H128F GND:7=GND VCC:14=+5V 1D — 74LS86: H1-H8 XOR FLIP (screen flip on H counter, low bits). FLIPb label printed only at 2D - the rail runs unlabelled through 1D pins 2/5/10/13 on to 6D — verified 2026-07-21 1D ✓ 74LS86 H4 · H counter bit · from CN-2 C6 A1 1 H4 $CFLIPb B1 2 $CFLIPb H1 · H counter bit 0 (pixel) · from CN-2 C5 A2 4 H1 $CFLIPb B2 5 $CFLIPb H8 · H counter bit · from CN-2 D6 A3 9 H8 $CFLIPb B3 10 $CFLIPb H2 · H counter bit · from CN-2 D5 A4 12 H2 $CFLIPb B4 13 $CFLIPb $H4F Y1 3 $H4F $H1F Y2 6 $H1F H8F · flip-XORed H bit (1D) Y3 8 H8F $H2F Y4 11 $H2F GND:7=GND VCC:14=+5V 9E — 74LS04: Inverter pack. FLIP (CN-2 D2) -> pin 4 = /$CFLIP (bare on the drawing, so the name is ours), which feeds 7E and is re-inverted twice: pin 6 = $CFLIPb (local, to 1D/2D/6D) and pin 10 = FLIPa (Capcom-lettered, alpha-suffixed, out to sheets 2/3 and 3/3 for the V-flip XORs). Both are FLIP restored, buffered separately. Also H256 -> /H256 and H1 -> /H1. — verified 2026-07-21 9E ✓ 74LS04 FLIP · screen flip register bit from the A board · from CN-2 D2 A2 3 FLIP /$CFLIP A3 5 /$CFLIP H256 · H counter bit 8 (line half) · from CN-2 C9 A4 9 H256 /$CFLIP A5 11 /$CFLIP H1 · H counter bit 0 (pixel) · from CN-2 C5 A6 13 H1 /$CFLIP Y2 4 /$CFLIP $CFLIPb Y3 6 $CFLIPb /H256 · inverted H256 (9E) -> 8E wrap gate + 5D B1 (adds 256 while H256 is low) Y4 8 /H256 FLIPa · re-buffered FLIP (9E) - the alpha copy used on the other sheets · to sheets 2/3 + 3/3 · Capcom letters this FLIP-alpha; our lowercase a is the alpha Y5 10 FLIPa /H1 · inverted H1 (9E) - clock for the phiSC divider Y6 12 /H1 GND:7=GND VCC:14=+5V 3D — 74LS283: Scroll X + H adder, low nibble: $SCX0-3 + $H1F-H8F -> SH8 direct + raw low sums to the 6D phase XORs — verified 2026-07-21 3D ✓ 74LS283 $H2F B2 2 $H2F $SCX1 A2 3 $SCX1 $SCX0 A1 5 $SCX0 $H1F B1 6 $H1F GND C0 7 GND H8F · flip-XORed H bit (1D) B4 11 H8F $SCX3 A4 12 $SCX3 $SCX2 A3 14 $SCX2 $H4F B3 15 $H4F $SH2R S2 1 $SH2R $SH1R S1 4 $SH1R $XC4 C4 9 $XC4 SH8 · scrolled H bit 3 (pixel-in-tile high bit) · to sheet 3/3 S4 10 SH8 $SH4R S3 13 $SH4R GND:8=GND VCC:16=+5V 4D — 74LS283: Scroll X + H adder, mid nibble: $SCX4-7 + H16F-H64F + corrected $H128C -> SH16-SH128 to 2/3 — verified 2026-07-21 4D ✓ 74LS283 H32F · flip-XORed H bit (2D) B2 2 H32F $SCX5 A2 3 $SCX5 $SCX4 A1 5 $SCX4 H16F · flip-XORed H bit (2D) B1 6 H16F $XC4 C0 7 $XC4 $H128C B4 11 $H128C $SCX7 A4 12 $SCX7 $SCX6 A3 14 $SCX6 H64F · flip-XORed H bit (2D) -> 4D B3 + the 7E correction XOR B3 15 H64F SH32 · scrolled H (tilemap column) · to sheet 2/3 S2 1 SH32 SH16 · scrolled H (tilemap column) · to sheet 2/3 S1 4 SH16 $XC8 C4 9 $XC8 SH128 · scrolled H (tilemap column) · to sheet 2/3 S4 10 SH128 SH64 · scrolled H (tilemap column) · to sheet 2/3 S3 13 SH64 GND:8=GND VCC:16=+5V 5D — 74LS283: Scroll X + H adder, high: $SCX8 + /H256 + carry -> SH256 to 2/3 (other sections grounded/unused) — verified 2026-07-21 5D ✓ 74LS283 GND B2 2 GND GND A2 3 GND $SCX8 A1 5 $SCX8 /H256 · inverted H256 (9E) -> 8E wrap gate + 5D B1 (adds 256 while H256 is low) B1 6 /H256 $XC8 C0 7 $XC8 GND B4 11 GND GND A4 12 GND GND A3 14 GND GND B3 15 GND SH256 · scrolled H (tilemap column, top bit) · to sheet 2/3 S1 4 SH256 GND:8=GND VCC:16=+5V 7E — 74LS86: Units on this sheet: H-wrap correction. H64F XOR /FLIP = /H64 (flip cancels out); then (/H64 AND /H256) XOR H128F -> corrected bit-7 into 4D B4 — verified 2026-07-21 7E ✓ 74LS86 drawn on c1-3-scrollrom - click to jump there · SH8 · scrolled H bit 3 (pixel-in-tile high bit) · to sheet 3/3 A1 1 SH8 ↗ drawn on c1-3-scrollrom - click to jump there · SHFLIP B1 2 SHFLIP ↗ drawn on c1-3-scrollrom - click to jump there · SHFLIPa B2 4 SHFLIPa ↗ drawn on c1-3-scrollrom - click to jump there · FLIPa · re-buffered FLIP (9E) - the alpha copy used on the other sheets · to sheets 2/3 + 3/3 · Capcom letters this FLIP-alpha; our lowercase a is the alpha A2 5 FLIPa ↗ H64F · flip-XORed H bit (2D) -> 4D B3 + the 7E correction XOR A3 9 H64F /$CFLIP B3 10 /$CFLIP $H256G A4 12 $H256G H128F · flip-XORed H bit (2D) -> only into the 7E correction XOR (4D B4 gets the corrected H128C) B4 13 H128F drawn on c1-3-scrollrom - click to jump there · $SH8X Y1 3 $SH8X ↗ drawn on c1-3-scrollrom - click to jump there · $FSFLIP Y2 6 $FSFLIP ↗ $H64X Y3 8 $H64X $H128C Y4 11 $H128C GND:7=GND VCC:14=+5V 8E — 74LS08: AND gates: S6M = 6M gated with +5 (buffer) -> 8D clock + sheets 2/3+3/3; H256 gating unit; phiSC clear gate — verified 2026-07-21 8E ✓ 74LS08 $D8CS · The phiSC clear gate. The drawing prints no pin numbers for this gate; settled by board inspection 2026-07-21: 8E pin 6 has no trace (gate 4,5->6 is the unused spare) and pin 3 routes to 9D (/CL2, pin 13). Which input carries DBCS vs LSCREN is interchangeable. | renamed 2026-07-27: same net as io 3B pin 7 /$D8CS (D800-DFFF, CN-1 B14) - was an 8 vs B split A1 1 $D8CS LSCREN · inverted grant (9D /Q), active low: selects CPU address + enables 3C on 2/3 · to sheet 2/3 B1 2 LSCREN $H64X A3 9 $H64X /H256 · inverted H256 (9E) -> 8E wrap gate + 5D B1 (adds 256 while H256 is low) B3 10 /H256 +5V B4 12 +5V 6M · 6 MHz pixel clock · from CN-2 C3 A4 13 6M $PHISCCL Y1 3 $PHISCCL $H256G Y3 8 $H256G S6M · buffered 6 MHz pixel clock (8E) - clocks 8D and the 4B pixel latch · to sheets 2/3 + 3/3 Y4 11 S6M GND:7=GND VCC:14=+5V 6D — 74LS86: Units on this sheet: low SH sum bits XOR FLIPb (phase order reverses on flip) -> 7D decoder inputs; SH2 also to 2/3 — verified 2026-07-21 6D ✓ 74LS86 $SH4R A1 1 $SH4R $CFLIPb B1 2 $CFLIPb $SH1R A2 4 $SH1R $CFLIPb B2 5 $CFLIPb $SH2R A3 9 $SH2R $CFLIPb B3 10 $CFLIPb drawn on c1-2-scrollvram - click to jump there · $YC8 B4 12 $YC8 ↗ drawn on c1-2-scrollvram - click to jump there · $SCY8 A4 13 $SCY8 ↗ $SH8P Y1 3 $SH8P SH2 · phase-corrected scrolled H (6D) - the A10 code/attr toggle on 2/3 + 7D A input · to sheet 2/3 Y2 6 SH2 $SH4P Y3 8 $SH4P drawn on c1-2-scrollvram - click to jump there · V256S Y4 11 V256S ↗ GND:7=GND VCC:14=+5V 7D — 74LS138: Sub-tile phase decoder (free-running, always enabled): counts the 8 pixel phases of each tile fetch — verified 2026-07-21 7D ✓ 74LS138 SH2 · phase-corrected scrolled H (6D) - the A10 code/attr toggle on 2/3 + 7D A input · to sheet 2/3 A 1 SH2 $SH4P B 2 $SH4P $SH8P C 3 $SH8P GND ~G2A 4 GND GND ~G2B 5 GND +5V G1 6 +5V /S7H · sub-tile phase 7 strobe (7D Y7) - shifter load on 3/3, also 8D D2 and the grant clock · to sheet 3/3 Y7 7 /S7H /$S3H Y3 12 /$S3H /$S1H Y1 14 /$S1H GND:8=GND VCC:16=+5V 8D — 74LS175: Scroll fetch strobe latch, clocked by S6M (dirty-board repair IC): /S7H//S3H//S1H -> S0H/S4H/S2H to 2/3 — verified 2026-07-21 8D ✓ 74LS175 +5V ~CL 1 +5V /S7H · sub-tile phase 7 strobe (7D Y7) - shifter load on 3/3, also 8D D2 and the grant clock · to sheet 3/3 D2 5 /S7H S6M · buffered 6 MHz pixel clock (8E) - clocks 8D and the 4B pixel latch · to sheets 2/3 + 3/3 CLK 9 S6M /$S3H D3 12 /$S3H /$S1H D4 13 /$S1H S0H · latched fetch strobe (8D /Q2) - clocks the 3B colour latch · to sheet 2/3 ~Q2 6 S0H S4H · latched fetch strobe (8D /Q3) - clocks the 3A attr latch on 2/3 and the 9D grant flip-flop · to sheet 2/3 ~Q3 11 S4H S2H · latched fetch strobe (8D /Q4) - clocks the 4A code latch · to sheet 2/3 ~Q4 14 S2H GND:8=GND VCC:16=+5V
· Original scan — manual p20 · zoom
original schematic scan
2A
9C
9D
4C
6C
2D
1D
9E
3D
4D
5D
7E
8E
6D
7D
8D