85605-C-1 Sheet 2/3 — SCROLL VIDEO RAM

manual p21 · 18 ICs · 18 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Interboard connectors (the band cables between the boards) — circled letter+number labels on the drawing are connector row + pin
5C — 74LS273: Scroll Y register low byte - CPU write C80A (POS2) — verified 2026-07-20 5C ✓ 74LS273 +5V ~CL 1 +5V DB7 · buffered CPU data bus (CN-1 A8) D1 3 DB7 DB6 · buffered CPU data bus (CN-1 A7) D2 4 DB6 DB5 · buffered CPU data bus (CN-1 A6) D3 7 DB5 DB4 · buffered CPU data bus (CN-1 A5) D4 8 DB4 POS2 · C80A write strobe (scroll Y low) · from sheet 1/3 CLK 11 POS2 DB3 · buffered CPU data bus (CN-1 A4) D5 13 DB3 DB2 · buffered CPU data bus (CN-1 A3) D6 14 DB2 DB1 · buffered CPU data bus (CN-1 A2) D7 17 DB1 DB0 · buffered CPU data bus (CN-1 A1) D8 18 DB0 $SCY7 Q1 2 $SCY7 $SCY6 Q2 5 $SCY6 $SCY5 Q3 6 $SCY5 $SCY4 Q4 9 $SCY4 $SCY3 Q5 12 $SCY3 $SCY2 Q6 15 $SCY2 $SCY1 Q7 16 $SCY1 $SCY0 Q8 19 $SCY0 GND:10=GND VCC:20=+5V 6C — 74LS74: Unit B on this sheet: scroll Y bit 8 - CPU write C80B (POS3) latches DB0 — verified 2026-07-20 6C ✓ 74LS74 +5V ~CL 1 +5V DB0 · buffered CPU data bus (CN-1 A1) D 2 DB0 POS3 · C80B write strobe (scroll Y bit 8) · from sheet 1/3 CLK 3 POS3 +5V ~PR 4 +5V drawn on c1-1-scrollh - click to jump there · +5V ~PR 10 +5V ↗ drawn on c1-1-scrollh - click to jump there · POS1 CLK 11 POS1 ↗ drawn on c1-1-scrollh - click to jump there · DB0 · buffered CPU data bus (CN-1 A1) D 12 DB0 ↗ drawn on c1-1-scrollh - click to jump there · +5V ~CL 13 +5V ↗ $SCY8 Q 5 $SCY8 drawn on c1-1-scrollh - click to jump there · $SCX8 Q 9 $SCX8 ↗ GND:7=GND VCC:14=+5V 1E — 74LS86: V1-V8 XOR FLIPa (screen flip on V counter, low bits; gate order V1/V8/V2/V4) — verified 2026-07-20 1E ✓ 74LS86 V1 · V counter bit · from CN-2 C10 A1 1 V1 FLIPa · screen-flip, drawn FLIP-alpha: the alpha suffix marks a buffered/re-latched copy (plain FLIP = the register bit, on sheet 1/3) · from sheet 1/3 · Capcom letters this FLIP-alpha; our lowercase a is the alpha B1 2 FLIPa V8 · V counter bit · from CN-2 D11 A2 4 V8 FLIPa · screen-flip, drawn FLIP-alpha: the alpha suffix marks a buffered/re-latched copy (plain FLIP = the register bit, on sheet 1/3) · from sheet 1/3 · Capcom letters this FLIP-alpha; our lowercase a is the alpha B2 5 FLIPa V2 · V counter bit · from CN-2 D10 A3 9 V2 FLIPa · screen-flip, drawn FLIP-alpha: the alpha suffix marks a buffered/re-latched copy (plain FLIP = the register bit, on sheet 1/3) · from sheet 1/3 · Capcom letters this FLIP-alpha; our lowercase a is the alpha B3 10 FLIPa V4 · V counter bit · from CN-2 C11 A4 12 V4 FLIPa · screen-flip, drawn FLIP-alpha: the alpha suffix marks a buffered/re-latched copy (plain FLIP = the register bit, on sheet 1/3) · from sheet 1/3 · Capcom letters this FLIP-alpha; our lowercase a is the alpha B4 13 FLIPa V1F · flip-XORed V bit Y1 3 V1F V8F · flip-XORed V bit Y2 6 V8F V2F · flip-XORed V bit Y3 8 V2F V4F · flip-XORed V bit Y4 11 V4F GND:7=GND VCC:14=+5V 2E — 74LS86: V16-V128 XOR FLIPa (screen flip on V counter, high bits; gate order V32/V16/V64/V128, V64 pin 9 by elimination) — verified 2026-07-20 2E ✓ 74LS86 V32 · V counter bit · from CN-2 D12 A1 1 V32 FLIPa · screen-flip, drawn FLIP-alpha: the alpha suffix marks a buffered/re-latched copy (plain FLIP = the register bit, on sheet 1/3) · from sheet 1/3 · Capcom letters this FLIP-alpha; our lowercase a is the alpha B1 2 FLIPa V16 · V counter bit · from CN-2 C12 A2 4 V16 FLIPa · screen-flip, drawn FLIP-alpha: the alpha suffix marks a buffered/re-latched copy (plain FLIP = the register bit, on sheet 1/3) · from sheet 1/3 · Capcom letters this FLIP-alpha; our lowercase a is the alpha B2 5 FLIPa V64 · V counter bit · from CN-2 C13 A3 9 V64 FLIPa · screen-flip, drawn FLIP-alpha: the alpha suffix marks a buffered/re-latched copy (plain FLIP = the register bit, on sheet 1/3) · from sheet 1/3 · Capcom letters this FLIP-alpha; our lowercase a is the alpha B3 10 FLIPa V128 · V counter bit · from CN-2 D13 A4 12 V128 FLIPa · screen-flip, drawn FLIP-alpha: the alpha suffix marks a buffered/re-latched copy (plain FLIP = the register bit, on sheet 1/3) · from sheet 1/3 · Capcom letters this FLIP-alpha; our lowercase a is the alpha B4 13 FLIPa V32F · flip-XORed V bit Y1 3 V32F V16F · flip-XORed V bit Y2 6 V16F V64F · flip-XORed V bit Y3 8 V64F V128F · flip-XORed V bit Y4 11 V128F GND:7=GND VCC:14=+5V 3E — 74LS273: Flipped-V latch, clocked by OH (CN-2 D3) — verified 2026-07-20 3E ✓ 74LS273 +5V ~CL 1 +5V V1F · flip-XORed V bit D1 3 V1F V2F · flip-XORed V bit D2 4 V2F V4F · flip-XORed V bit D3 7 V4F V8F · flip-XORed V bit D4 8 V8F OH · row latch clock from A board · from CN-2 D3 CLK 11 OH V16F · flip-XORed V bit D5 13 V16F V32F · flip-XORed V bit D6 14 V32F V64F · flip-XORed V bit D7 17 V64F V128F · flip-XORed V bit D8 18 V128F $V1L Q1 2 $V1L $V2L Q2 5 $V2L $V4L Q3 6 $V4L $V8L Q4 9 $V8L $V16L Q5 12 $V16L $V32L Q6 15 $V32L $V64L Q7 16 $V64L $V128L Q8 19 $V128L GND:10=GND VCC:20=+5V 5E — 74LS283: Scroll Y + V adder, low nibble -> V1S-V8S — verified 2026-07-20 5E ✓ 74LS283 $V2L B2 2 $V2L $SCY1 A2 3 $SCY1 $SCY0 A1 5 $SCY0 $V1L B1 6 $V1L GND C0 7 GND $V8L B4 11 $V8L $SCY3 A4 12 $SCY3 $SCY2 A3 14 $SCY2 $V4L B3 15 $V4L V2S · scrolled V · to sheet 3/3 S2 1 V2S V1S · scrolled V (row-in-tile) · to sheet 3/3 S1 4 V1S $YC4 C4 9 $YC4 V8S · scrolled V · to sheet 3/3 S4 10 V8S V4S · scrolled V · to sheet 3/3 S3 13 V4S GND:8=GND VCC:16=+5V 4E — 74LS283: Scroll Y + V adder, high nibble -> V16S-V128S (dirty-board repair: pin 13 stuck low) — verified 2026-07-20 4E ✓ 74LS283 $V32L B2 2 $V32L $SCY5 A2 3 $SCY5 $SCY4 A1 5 $SCY4 $V16L B1 6 $V16L $YC4 C0 7 $YC4 $V128L B4 11 $V128L $SCY7 A4 12 $SCY7 $SCY6 A3 14 $SCY6 $V64L B3 15 $V64L V32S · scrolled V (tilemap row) S2 1 V32S V16S · scrolled V (tilemap row) S1 4 V16S $YC8 C4 9 $YC8 V128S · scrolled V (tilemap row) S4 10 V128S V64S · scrolled V (tilemap row) S3 13 V64S GND:8=GND VCC:16=+5V 6D — 74LS86: Unit on this sheet: V256S = $SCY8 (6C pin 5) XOR adder carry $YC8 (4E pin 9) - bit 9 of scroll Y + V — verified 2026-07-20 6D ✓ 74LS86 drawn on c1-1-scrollh - click to jump there · $SH4R A1 1 $SH4R ↗ drawn on c1-1-scrollh - click to jump there · $CFLIPb B1 2 $CFLIPb ↗ drawn on c1-1-scrollh - click to jump there · $SH1R A2 4 $SH1R ↗ drawn on c1-1-scrollh - click to jump there · $CFLIPb B2 5 $CFLIPb ↗ drawn on c1-1-scrollh - click to jump there · $SH2R A3 9 $SH2R ↗ drawn on c1-1-scrollh - click to jump there · $CFLIPb B3 10 $CFLIPb ↗ $YC8 B4 12 $YC8 $SCY8 A4 13 $SCY8 drawn on c1-1-scrollh - click to jump there · $SH8P Y1 3 $SH8P ↗ drawn on c1-1-scrollh - click to jump there · SH2 · scrolled H · from sheet 1/3 Y2 6 SH2 ↗ drawn on c1-1-scrollh - click to jump there · $SH4P Y3 8 $SH4P ↗ V256S · scrolled V (tilemap row bit 9) - derived on this board by 6D (SCY8 XOR adder carry), NOT an interboard signal: the scroll register makes the tilemap logically taller than the 256-line screen Y4 11 V256S GND:7=GND VCC:14=+5V 2B — M58725: bg VRAM 2kB (D800-DBFF code / DC00-DFFF attr). MB8416/6116 on the physical board; both boards had this RAM replaced. ~CE and ~OE hard-grounded (always on; a write releases the outputs). NB manual prints the GND pin as '14' - typo, GND is pin 12 (14 is D4) — verified 2026-07-20 2B ✓ M58725 $MA7 A7 1 $MA7 $MA6 A6 2 $MA6 $MA5 A5 3 $MA5 $MA4 A4 4 $MA4 $MA3 A3 5 $MA3 $MA2 A2 6 $MA2 $MA1 A1 7 $MA1 $MA0 A0 8 $MA0 GND ~CE 18 GND $MA10 A10 19 $MA10 GND ~OE 20 GND /$VRAMWR ~WE 21 /$VRAMWR $MA9 A9 22 $MA9 $MA8 A8 23 $MA8 DF0 · C-board VRAM data bus D0 9 DF0 DF1 · C-board VRAM data bus D1 10 DF1 DF2 · C-board VRAM data bus D2 11 DF2 DF3 · C-board VRAM data bus D3 13 DF3 DF4 · C-board VRAM data bus D4 14 DF4 DF5 · C-board VRAM data bus D5 15 DF5 DF6 · C-board VRAM data bus D6 16 DF6 DF7 · C-board VRAM data bus D7 17 DF7 GND:12=GND VCC:24=+5V 1A — 74LS157: VRAM address/write mux: A8-A10 + /WE (section 4 muxes /$CPUWR vs +5 = the VRAM write gate) — verified 2026-07-20 1A ✓ 74LS157 LSCREN · latched access grant, active low: low = CPU window (drives 1A/1B/1C SEL to the CPU-address side and enables the 3C '245) · from sheet 1/3 SEL 1 LSCREN AB8 · buffered CPU address (CN-1 A21) 1A 2 AB8 SH128 · scrolled H · from sheet 1/3 1B 3 SH128 AB9 · buffered CPU address (CN-1 A22) 2A 5 AB9 SH256 · scrolled H · from sheet 1/3 2B 6 SH256 SH2 · scrolled H · from sheet 1/3 3B 10 SH2 AB10 · buffered CPU address (CN-1 A23) 3A 11 AB10 +5V 4B 13 +5V /$CPUWR 4A 14 /$CPUWR GND ~ST 15 GND $MA8 1Y 4 $MA8 $MA9 2Y 7 $MA9 $MA10 3Y 9 $MA10 /$VRAMWR 4Y 12 /$VRAMWR GND:8=GND VCC:16=+5V 1B — 74LS157: VRAM address mux: A4-A7 (V256S row bit + tile column SH16-SH64) — verified 2026-07-20 1B ✓ 74LS157 LSCREN · latched access grant, active low: low = CPU window (drives 1A/1B/1C SEL to the CPU-address side and enables the 3C '245) · from sheet 1/3 SEL 1 LSCREN AB4 · buffered CPU address (CN-1 A17) 1A 2 AB4 V256S · scrolled V (tilemap row bit 9) - derived on this board by 6D (SCY8 XOR adder carry), NOT an interboard signal: the scroll register makes the tilemap logically taller than the 256-line screen 1B 3 V256S AB5 · buffered CPU address (CN-1 A18) 2A 5 AB5 SH16 · scrolled H (tilemap column) · from sheet 1/3 2B 6 SH16 SH32 · scrolled H · from sheet 1/3 3B 10 SH32 AB6 · buffered CPU address (CN-1 A19) 3A 11 AB6 SH64 · scrolled H · from sheet 1/3 4B 13 SH64 AB7 · buffered CPU address (CN-1 A20) 4A 14 AB7 GND ~ST 15 GND $MA4 1Y 4 $MA4 $MA5 2Y 7 $MA5 $MA6 3Y 9 $MA6 $MA7 4Y 12 $MA7 GND:8=GND VCC:16=+5V 1C — 74LS157: VRAM address mux: A0-A3 (tile row V16S-V128S) - display address is column-major, matches MAME TILEMAP_SCAN_COLS — verified 2026-07-20 1C ✓ 74LS157 LSCREN · latched access grant, active low: low = CPU window (drives 1A/1B/1C SEL to the CPU-address side and enables the 3C '245) · from sheet 1/3 SEL 1 LSCREN AB0 · buffered CPU address (CN-1 A13) 1A 2 AB0 V16S · scrolled V (tilemap row) 1B 3 V16S AB1 · buffered CPU address (CN-1 A14) 2A 5 AB1 V32S · scrolled V (tilemap row) 2B 6 V32S V64S · scrolled V (tilemap row) 3B 10 V64S AB2 · buffered CPU address (CN-1 A15) 3A 11 AB2 V128S · scrolled V (tilemap row) 4B 13 V128S AB3 · buffered CPU address (CN-1 A16) 4A 14 AB3 GND ~ST 15 GND $MA0 1Y 4 $MA0 $MA1 2Y 7 $MA1 $MA2 3Y 9 $MA2 $MA3 4Y 12 $MA3 GND:8=GND VCC:16=+5V 2C — 74LS00: Write qualifier: NAND(/RDB, SCREN) -> gated CPU write strobe — verified 2026-07-20 2C ✓ 74LS00 /RDB · buffered CPU read strobe · from CN-1 B25 A1 1 /RDB SCREN · CPU VRAM access grant · from sheet 1/3 B1 2 SCREN /$CPUWR Y1 3 /$CPUWR GND:7=GND VCC:14=+5V 3C — 74LS245: CPU data window: local VRAM bus DF <-> interboard DB — verified 2026-07-20 3C ✓ 74LS245 /RDB · buffered CPU read strobe · from CN-1 B25 DIR 1 /RDB DB0 · buffered CPU data bus (CN-1 A1) A1 2 DB0 DB1 · buffered CPU data bus (CN-1 A2) A2 3 DB1 DB2 · buffered CPU data bus (CN-1 A3) A3 4 DB2 DB3 · buffered CPU data bus (CN-1 A4) A4 5 DB3 DB4 · buffered CPU data bus (CN-1 A5) A5 6 DB4 DB5 · buffered CPU data bus (CN-1 A6) A6 7 DB5 DB6 · buffered CPU data bus (CN-1 A7) A7 8 DB6 DB7 · buffered CPU data bus (CN-1 A8) A8 9 DB7 LSCREN · latched access grant, active low: low = CPU window (drives 1A/1B/1C SEL to the CPU-address side and enables the 3C '245) · from sheet 1/3 ~EN 19 LSCREN DF7 · C-board VRAM data bus B8 11 DF7 DF6 · C-board VRAM data bus B7 12 DF6 DF5 · C-board VRAM data bus B6 13 DF5 DF4 · C-board VRAM data bus B5 14 DF4 DF3 · C-board VRAM data bus B4 15 DF3 DF2 · C-board VRAM data bus B3 16 DF2 DF1 · C-board VRAM data bus B2 17 DF1 DF0 · C-board VRAM data bus B1 18 DF0 GND:10=GND VCC:20=+5V 4A — 74LS273: Tile code latch: DF -> AS0-AS7 (to sheet 3/3 ROM address), clocked by S2H — verified 2026-07-20 4A ✓ 74LS273 +5V ~CL 1 +5V DF0 · C-board VRAM data bus D1 3 DF0 DF1 · C-board VRAM data bus D2 4 DF1 DF2 · C-board VRAM data bus D3 7 DF2 DF3 · C-board VRAM data bus D4 8 DF3 S2H · code latch strobe · from sheet 1/3 (8D '175) CLK 11 S2H DF4 · C-board VRAM data bus D5 13 DF4 DF5 · C-board VRAM data bus D6 14 DF5 DF6 · C-board VRAM data bus D7 17 DF6 DF7 · C-board VRAM data bus D8 18 DF7 AS0 · tile code · to sheet 3/3 Q1 2 AS0 AS1 · tile code · to sheet 3/3 Q2 5 AS1 AS2 · tile code · to sheet 3/3 Q3 6 AS2 AS3 · tile code · to sheet 3/3 Q4 9 AS3 AS4 · tile code · to sheet 3/3 Q5 12 AS4 AS5 · tile code · to sheet 3/3 Q6 15 AS5 AS6 · tile code · to sheet 3/3 Q7 16 AS6 AS7 · tile code · to sheet 3/3 Q8 19 AS7 GND:10=GND VCC:20=+5V 3A — 74LS273: Attribute latch: DF -> color bits (to 3B), flips, AS8/AS9, clocked by S4H — verified 2026-07-20 3A ✓ 74LS273 +5V ~CL 1 +5V DF0 · C-board VRAM data bus D1 3 DF0 DF1 · C-board VRAM data bus D2 4 DF1 DF2 · C-board VRAM data bus D3 7 DF2 DF3 · C-board VRAM data bus D4 8 DF3 S4H · attr latch strobe · from sheet 1/3 (8D '175) CLK 11 S4H DF4 · C-board VRAM data bus D5 13 DF4 DF5 · C-board VRAM data bus D6 14 DF5 DF6 · C-board VRAM data bus D7 17 DF6 DF7 · C-board VRAM data bus D8 18 DF7 $AT0 Q1 2 $AT0 $AT1 Q2 5 $AT1 $AT2 Q3 6 $AT2 $AT3 Q4 9 $AT3 SHFLIP · tile H flip (attr); also re-latched by 3B into SHFLIPa · to sheet 3/3 Q5 12 SHFLIP SVFLIP · tile V flip (attr) · to sheet 3/3 Q6 15 SVFLIP AS8 · tile code (attr bit 6) · to sheet 3/3 Q7 16 AS8 AS9 · tile code bank (attr bit 7) · to sheet 3/3 Q8 19 AS9 GND:10=GND VCC:20=+5V 3B — 74LS174: S0H re-latch: colour code $AT0-3 -> SCD0-3 plus SHFLIP -> SHFLIPa (pixel-aligned copy). Dirty-board colour repair — verified 2026-07-20 3B ✓ 74LS174 +5V ~CL 1 +5V $AT0 D1 3 $AT0 $AT1 D2 4 $AT1 $AT2 D3 6 $AT2 S0H · scroll fetch strobe · from sheet 1/3 (8D '175) CLK 9 S0H SHFLIP · tile H flip (attr); also re-latched by 3B into SHFLIPa · to sheet 3/3 D4 11 SHFLIP $AT3 D5 13 $AT3 SCD0 · bg color code bit Q1 2 SCD0 SCD1 · bg color code bit Q2 5 SCD1 SCD2 · bg color code bit Q3 7 SCD2 SHFLIPa · SHFLIP re-latched by S0H (3B FF4) - pixel-aligned copy; drawn SHFLIP-alpha · to sheet 3/3 Q4 10 SHFLIPa SCD3 · bg color code bit Q5 12 SCD3 GND:8=GND VCC:16=+5V 4B — 74LS273: Final bg pixel latch, clocked by S6M: SCRX/Y/Z (pixel planes from 7C '157 on 3/3) -> SCRC/B/A + SCD0-3 (colour) -> SCRD-G, out to the A board mixer. FF 8->9 unused — verified 2026-07-20 4B ✓ 74LS273 +5V ~CL 1 +5V SCRX · bg pixel bit (X plane) · from sheet 3/3 (7C '157) D1 3 SCRX SCRY · bg pixel bit (Y plane) · from sheet 3/3 (7C '157) D2 4 SCRY SCRZ · bg pixel bit (Z plane) · from sheet 3/3 (7C '157) D3 7 SCRZ S6M · 6 MHz pixel clock (gated) · from sheet 1/3 CLK 11 S6M SCD3 · bg color code bit D5 13 SCD3 SCD2 · bg color code bit D6 14 SCD2 SCD1 · bg color code bit D7 17 SCD1 SCD0 · bg color code bit D8 18 SCD0 SCRC · bg color index out · to CN-2 C1 Q1 2 SCRC SCRB · bg color index out · to CN-2 D1 Q2 5 SCRB SCRA · bg color index out · to CN-2 C2 -> A board mixer Q3 6 SCRA SCRG · bg color index out (7th bit) · to CN-1 B12 Q5 12 SCRG SCRF · bg color index out · to CN-1 B18 Q6 15 SCRF SCRE · bg color index out · to CN-1 B17 Q7 16 SCRE SCRD · bg color index out · to CN-1 B16 Q8 19 SCRD GND:10=GND VCC:20=+5V
· Original scan — manual p21 · zoom
original schematic scan
5C
6C
1E
2E
3E
5E
4E
6D
2B
1A
1B
1C
2C
3C
4A
3A
3B
4B