85605-C-1 Sheet 3/3 — SCROLL ROM

manual p22 · 17 ICs · 17 verified ✓ · layout mirrors the original drawing
Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
6E — 74LS86: Tile-row address flip: V1S-V8S XOR SVFLIP (scroll V flip from 2/3) -> ROM A0-A3 (row within the 16px tile). All four units used — verified 2026-07-21 6E ✓ 74LS86 V2S A1 1 V2S SVFLIP B1 2 SVFLIP V1S A2 4 V1S SVFLIP B2 5 SVFLIP V4S A3 9 V4S SVFLIP B3 10 SVFLIP V8S A4 12 V8S SVFLIP B4 13 SVFLIP $SV2 Y1 3 $SV2 $SV1 Y2 6 $SV1 $SV4 Y3 8 $SV4 $SV8 Y4 11 $SV8 GND:7=GND VCC:14=+5V 7E — 74LS86: Units on this sheet: SH8 XOR SHFLIP -> ROM A4 (left/right tile half); FLIPa XOR SHFLIPa -> $FSFLIP (net flip state driving shift direction + output mux) — verified 2026-07-21 7E ✓ 74LS86 SH8 A1 1 SH8 SHFLIP B1 2 SHFLIP SHFLIPa B2 4 SHFLIPa FLIPa · Capcom letters this FLIP-alpha; our lowercase a is the alpha A2 5 FLIPa drawn on c1-1-scrollh - click to jump there · H64F A3 9 H64F ↗ drawn on c1-1-scrollh - click to jump there · /$CFLIP B3 10 /$CFLIP ↗ drawn on c1-1-scrollh - click to jump there · $H256G A4 12 $H256G ↗ drawn on c1-1-scrollh - click to jump there · H128F B4 13 H128F ↗ $SH8X Y1 3 $SH8X $FSFLIP Y2 6 $FSFLIP drawn on c1-1-scrollh - click to jump there · $H64X Y3 8 $H64X ↗ drawn on c1-1-scrollh - click to jump there · $H128C Y4 11 $H128C ↗ GND:7=GND VCC:14=+5V 9C — 74LS04: Units on this sheet: /$AS9 inverter (ROM bank select for the second 27128 of each plane); /$S7H inverter -> $S7H; $FSFLIP inverter -> /$FSFLIP — verified 2026-07-21 9C ✓ 74LS04 /S7H A1 1 /S7H AS9 A2 3 AS9 drawn on c1-1-scrollh - click to jump there · /D8CS · renamed 2026-07-27: same net as io 3B pin 7 /$D8CS (D800-DFFF, CN-1 B14) - was an 8 vs B split A3 5 /D8CS ↗ $FSFLIP A6 13 $FSFLIP $S7H Y1 2 $S7H /$AS9 Y2 4 /$AS9 drawn on c1-1-scrollh - click to jump there · $D8CS · renamed 2026-07-27: same net as io 3B pin 7 /$D8CS (D800-DFFF, CN-1 B14) - was an 8 vs B split Y3 6 $D8CS ↗ /$FSFLIP Y6 12 /$FSFLIP GND:7=GND VCC:14=+5V 5A — 27128: SCR X plane tile ROM, bank 0 (/$AS9=1 selects) - MAME vt11.5a. NOTE reversed data order: D7->X0 ... D0->X7 — verified 2026-07-21 5A ✓ 27128 AS7 A12 2 AS7 AS2 A7 3 AS2 AS1 A6 4 AS1 AS0 A5 5 AS0 $SH8X A4 6 $SH8X $SV8 A3 7 $SV8 $SV4 A2 8 $SV4 $SV2 A1 9 $SV2 $SV1 A0 10 $SV1 AS9 ~CE 20 AS9 AS5 A10 21 AS5 GND ~OE 22 GND AS6 A11 23 AS6 AS4 A9 24 AS4 AS3 A8 25 AS3 AS8 A13 26 AS8 X7 D0 11 X7 X6 D1 12 X6 X5 D2 13 X5 X4 D3 15 X4 X3 D4 16 X3 X2 D5 17 X2 X1 D6 18 X1 X0 D7 19 X0 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 6A — 27128: SCR X plane tile ROM, bank 1 (/$AS9 selects) - MAME vt12.6a. Shares the full address + data bus with 5A (drawn as '27128 x 2') — verified 2026-07-21 6A ✓ 27128 AS7 A12 2 AS7 AS2 A7 3 AS2 AS1 A6 4 AS1 AS0 A5 5 AS0 $SH8X A4 6 $SH8X $SV8 A3 7 $SV8 $SV4 A2 8 $SV4 $SV2 A1 9 $SV2 $SV1 A0 10 $SV1 /$AS9 ~CE 20 /$AS9 AS5 A10 21 AS5 GND ~OE 22 GND AS6 A11 23 AS6 AS4 A9 24 AS4 AS3 A8 25 AS3 AS8 A13 26 AS8 X7 D0 11 X7 X6 D1 12 X6 X5 D2 13 X5 X4 D3 15 X4 X3 D4 16 X3 X2 D5 17 X2 X1 D6 18 X1 X0 D7 19 X0 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 7A — 27128: SCR Y plane tile ROM, bank 0 - MAME vt13.7a. Same bus pattern as the X pair; data reversed D7->Y0 ... D0->Y7 — verified 2026-07-21 7A ✓ 27128 AS7 A12 2 AS7 AS2 A7 3 AS2 AS1 A6 4 AS1 AS0 A5 5 AS0 $SH8X A4 6 $SH8X $SV8 A3 7 $SV8 $SV4 A2 8 $SV4 $SV2 A1 9 $SV2 $SV1 A0 10 $SV1 AS9 ~CE 20 AS9 AS5 A10 21 AS5 GND ~OE 22 GND AS6 A11 23 AS6 AS4 A9 24 AS4 AS3 A8 25 AS3 AS8 A13 26 AS8 Y7 D0 11 Y7 Y6 D1 12 Y6 Y5 D2 13 Y5 Y4 D3 15 Y4 Y3 D4 16 Y3 Y2 D5 17 Y2 Y1 D6 18 Y1 Y0 D7 19 Y0 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 8A — 27128: SCR Y plane tile ROM, bank 1 - MAME vt14.8a. Shares the full bus with 7A — verified 2026-07-21 8A ✓ 27128 AS7 A12 2 AS7 AS2 A7 3 AS2 AS1 A6 4 AS1 AS0 A5 5 AS0 $SH8X A4 6 $SH8X $SV8 A3 7 $SV8 $SV4 A2 8 $SV4 $SV2 A1 9 $SV2 $SV1 A0 10 $SV1 /$AS9 ~CE 20 /$AS9 AS5 A10 21 AS5 GND ~OE 22 GND AS6 A11 23 AS6 AS4 A9 24 AS4 AS3 A8 25 AS3 AS8 A13 26 AS8 Y7 D0 11 Y7 Y6 D1 12 Y6 Y5 D2 13 Y5 Y4 D3 15 Y4 Y3 D4 16 Y3 Y2 D5 17 Y2 Y1 D6 18 Y1 Y0 D7 19 Y0 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 9A — 27128: SCR Z plane tile ROM, bank 0 - MAME vt15.9a. Carries the power block for the ROM group on the drawing (VCC/~PGM/VPP=+5, ~OE/GND=GND) — verified 2026-07-21 9A ✓ 27128 AS7 A12 2 AS7 AS2 A7 3 AS2 AS1 A6 4 AS1 AS0 A5 5 AS0 $SH8X A4 6 $SH8X $SV8 A3 7 $SV8 $SV4 A2 8 $SV4 $SV2 A1 9 $SV2 $SV1 A0 10 $SV1 AS9 ~CE 20 AS9 AS5 A10 21 AS5 GND ~OE 22 GND AS6 A11 23 AS6 AS4 A9 24 AS4 AS3 A8 25 AS3 AS8 A13 26 AS8 Z7 D0 11 Z7 Z6 D1 12 Z6 Z5 D2 13 Z5 Z4 D3 15 Z4 Z3 D4 16 Z3 Z2 D5 17 Z2 Z1 D6 18 Z1 Z0 D7 19 Z0 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 10A — 27128: SCR Z plane tile ROM, bank 1 - MAME vt16.10a. Shares the full bus with 9A — verified 2026-07-21 10A ✓ 27128 AS7 A12 2 AS7 AS2 A7 3 AS2 AS1 A6 4 AS1 AS0 A5 5 AS0 $SH8X A4 6 $SH8X $SV8 A3 7 $SV8 $SV4 A2 8 $SV4 $SV2 A1 9 $SV2 $SV1 A0 10 $SV1 /$AS9 ~CE 20 /$AS9 AS5 A10 21 AS5 GND ~OE 22 GND AS6 A11 23 AS6 AS4 A9 24 AS4 AS3 A8 25 AS3 AS8 A13 26 AS8 Z7 D0 11 Z7 Z6 D1 12 Z6 Z5 D2 13 Z5 Z4 D3 15 Z4 Z3 D4 16 Z3 Z2 D5 17 Z2 Z1 D6 18 Z1 Z0 D7 19 Z0 VPP:1=+5V GND:14=GND ~PGM:27=+5V VCC:28=+5V 5B — 74LS194A: X plane shifter, low nibble (X0-X3). Normal-direction serial out QA -> 7C; cascades with 6B both ways for the 8-pixel byte — verified 2026-07-21 5B ✓ 74LS194A +5V ~CL 1 +5V GND SR 2 GND X0 A 3 X0 X1 B 4 X1 X2 C 5 X2 X3 D 6 X3 $XCAS2 SL 7 $XCAS2 $SSEL0 S0 9 $SSEL0 $SSEL1 S1 10 $SSEL1 S6M CLK 11 S6M $XCAS1 QD 12 $XCAS1 $XQA QA 15 $XQA GND:8=GND VCC:16=+5V 6B — 74LS194A: X plane shifter, high nibble (X4-X7). Flipped-direction serial out QD -> 7C — verified 2026-07-21 6B ✓ 74LS194A +5V ~CL 1 +5V $XCAS1 SR 2 $XCAS1 X4 A 3 X4 X5 B 4 X5 X6 C 5 X6 X7 D 6 X7 GND SL 7 GND $SSEL0 S0 9 $SSEL0 $SSEL1 S1 10 $SSEL1 S6M CLK 11 S6M $XQD QD 12 $XQD $XCAS2 QA 15 $XCAS2 GND:8=GND VCC:16=+5V 7B — 74LS194A: Y plane shifter, low nibble (Y0-Y3). QA -> 7C — verified 2026-07-21 7B ✓ 74LS194A +5V ~CL 1 +5V GND SR 2 GND Y0 A 3 Y0 Y1 B 4 Y1 Y2 C 5 Y2 Y3 D 6 Y3 $YCAS2 SL 7 $YCAS2 $SSEL0 S0 9 $SSEL0 $SSEL1 S1 10 $SSEL1 S6M CLK 11 S6M $YCAS1 QD 12 $YCAS1 $YQA QA 15 $YQA GND:8=GND VCC:16=+5V 8B — 74LS194A: Y plane shifter, high nibble (Y4-Y7). QD -> 7C — verified 2026-07-21 8B ✓ 74LS194A +5V ~CL 1 +5V $YCAS1 SR 2 $YCAS1 Y4 A 3 Y4 Y5 B 4 Y5 Y6 C 5 Y6 Y7 D 6 Y7 GND SL 7 GND $SSEL0 S0 9 $SSEL0 $SSEL1 S1 10 $SSEL1 S6M CLK 11 S6M $YQD QD 12 $YQD $YCAS2 QA 15 $YCAS2 GND:8=GND VCC:16=+5V 9B — 74LS194A: Z plane shifter, low nibble (Z0-Z3). QA -> 7C — verified 2026-07-21 9B ✓ 74LS194A +5V ~CL 1 +5V GND SR 2 GND Z0 A 3 Z0 Z1 B 4 Z1 Z2 C 5 Z2 Z3 D 6 Z3 $ZCAS2 SL 7 $ZCAS2 $SSEL0 S0 9 $SSEL0 $SSEL1 S1 10 $SSEL1 S6M CLK 11 S6M $ZCAS1 QD 12 $ZCAS1 $ZQA QA 15 $ZQA GND:8=GND VCC:16=+5V 10B — 74LS194A: Z plane shifter, high nibble (Z4-Z7). QD -> 7C — verified 2026-07-21 10B ✓ 74LS194A +5V ~CL 1 +5V $ZCAS1 SR 2 $ZCAS1 Z4 A 3 Z4 Z5 B 4 Z5 Z6 C 5 Z6 Z7 D 6 Z7 GND SL 7 GND $SSEL0 S0 9 $SSEL0 $SSEL1 S1 10 $SSEL1 S6M CLK 11 S6M $ZQD QD 12 $ZQD $ZCAS2 QA 15 $ZCAS2 GND:8=GND VCC:16=+5V 10C — 74LS32: Shifter mode gates: $S7H (load pulse) OR'd with $FSFLIP //FSFLIP -> S0/S1 of all six '194s. Load (11) during $S7H; shift left (10, QA-first) when unflipped; shift right (01, QD-first) when flipped — verified 2026-07-21 10C ✓ 74LS32 $S7H A1 1 $S7H $FSFLIP B1 2 $FSFLIP /$FSFLIP B4 12 /$FSFLIP $S7H A4 13 $S7H $SSEL0 · walkthrough-confirmed 2026-07-21: pin 3 -> S0 rail (pin 9s), pin 11 -> S1 rail (pin 10s), on all six '194s Y1 3 $SSEL0 $SSEL1 Y4 11 $SSEL1 GND:7=GND VCC:14=+5V 7C — 74LS157: Output tap mux: picks QA (normal) or QD (flipped) serial stream per plane -> SCRX/SCRY/SCRZ, the 3bpp background pixel to 2/3 (4B latch). Section 2 (pins 5,6,7) unused — verified 2026-07-21 7C ✓ 74LS157 $FSFLIP · walkthrough-confirmed 2026-07-21: SEL fed straight from 7E pin 6 (FLIPa XOR SHFLIPa) - selects the QD taps when flip is active SEL 1 $FSFLIP $ZQA 1A 2 $ZQA $ZQD 1B 3 $ZQD $XQD 3B 10 $XQD $XQA · REVIEW: A/B order derived, not printed clearly: A inputs = QA taps (normal, pixel 0 first), B inputs = QD taps (flipped). Same order assumed for the Y pair (14/13) and Z pair (2/3) 3A 11 $XQA $YQD 4B 13 $YQD $YQA 4A 14 $YQA GND ~ST 15 GND SCRZ 1Y 4 SCRZ SCRX 3Y 9 SCRX SCRY 4Y 12 SCRY GND:8=GND VCC:16=+5V
· Original scan — manual p22 · zoom
original schematic scan
6E
7E
9C
5A
6A
7A
8A
9A
10A
5B
6B
7B
8B
9B
10B
10C
7C