IC inventory

27128×17

16K x 8 EPROM. The graphics store: background tile ROMs on the C board, sprite bitmap ROMs on the B board, character shapes on the A board.

2114×6

1K x 4 static RAM. Used in pairs to make a byte wide - the 96-object sprite entry store and the sprite work RAM.

TBP24S10×6

256 x 4 bipolar PROM (7611). Look-up tables burned at the factory: the colour palette on the A board, the interrupt table on the CPU sheet, and the sprite line-timing PROM that defines the whole 24/96 object sequence.

2148H×4

1K x 4 static RAM, faster than the 2114. The two sprite line buffers: a pair per buffer, addressed by the 9-bit X counter, with bit 8 wired to /CE so sprites clip at the right edge.

M58725×3

2K x 8 static RAM. Work and video RAM.

27256×1

32K x 8 EPROM. The main program ROM. On the clean board this socket holds two stacked 27128s instead, split by address.

HM6264P×1

8K x 8 static RAM.

YM2203×2

FM + PSG sound chip (OPN). Two of them, addressed at 8000-8003. Wired write-only here - /RD is tied high and /WR grounded, so accesses are timed purely by chip select.

YM3014×2

Serial DAC. Converts each YM2203's FM output to analogue for the amplifier.

Z80A×2

8-bit CPU. Two of them: the main CPU at 11M, and a dedicated sound CPU at 11F that does nothing but drive the two YM2203s.

HA1368×1

Audio power amplifier. Drives the cabinet speaker.

LM324×1

Quad op-amp. Mixing and filtering the PSG and FM channels on the main amp sheet.

74LS273×14

Octal D flip-flop with clear. Byte-wide registers - sprite attributes, scroll position, colour output.

74LS174×12

Hex D flip-flop. Timing and pixel latches.

74LS194A×12

4-bit bidirectional shift register. The pixel shifters that serialise tile and sprite bitmaps, shifting either direction so a flipped graphic comes out reversed.

74LS161×9

4-bit synchronous counter with asynchronous clear. The H and V video counters that generate the whole raster.

74LS163×6

4-bit synchronous counter with synchronous clear. The sprite line-buffer X counters, three cascaded into a 9-bit count.

74LS175×3

Quad D flip-flop with complementary outputs.

74LS374×2

Octal D flip-flop with tri-state outputs. The sound-command mailbox between the two CPUs.

74LS373×1

Octal transparent latch.

74LS86×20

Quad XOR. The flip logic: XORing a counter against FLIP mirrors the screen, which is how the cocktail cabinet flips the picture for player two.

74LS74×14

Dual D flip-flop. Sync and blanking latches, the interrupt chain, the DMA handshake.

74LS04×10

Hex inverter. Also used throughout as a buffer, and as the source of the alpha/beta copies of FLIP, V1 and the pixel clock.

74LS08×9

Quad 2-input AND.

74LS32×7

Quad 2-input OR. Occasionally used with both inputs tied as a plain buffer.

74LS00×4

Quad 2-input NAND.

74LS20×4

Dual 4-input NAND. One of them (1L on the B board) is the sprite transparency test - a gate per line buffer, drawn on two different sheets.

74LS10×2

Triple 3-input NAND.

74LS112×1

Dual JK flip-flop. The horizontal blanking latch.

74LS14×1

Hex Schmitt-trigger inverter. Cleans up slow edges.

74LS30×1

8-input NAND. Decodes the V counter reaching line 248 to set the VSYNC latch.

74LS157×14

Quad 2-to-1 multiplexer. Switches video RAM address between the CPU and the display counters.

74LS245×12

Octal bidirectional bus transceiver. Bus isolation, and the direction reversal that lets the B board read sprite data out of the A board's RAM during blanking.

74LS138×8

3-to-8 line decoder. Address decoding and the read/write strobes.

74LS257×7

Quad 2-to-1 multiplexer with tri-state outputs. The line-buffer write-back and playback muxes.

74LS367×6

Hex buffer with tri-state outputs. Reading the control panel and DIP switches onto the data bus, and timing fan-out.

74LS139×5

Dual 2-to-4 line decoder. Region decoding and the line-buffer strobes.

74LS153×3

Dual 4-to-1 multiplexer. The colour mixer's priority selection between sprite, character and background pixels.

74LS283×13

4-bit binary full adder. Adds the scroll offset to the raw counter on the C board, and the sprite Y offset on the B board.

DIP-SW8×2

8-position DIP switch block. The two operator setting banks, read back through the '245s at 2A and 2B.

CUSTOM DIP48×1

Capcom's 48-pin opcode decryptor at 10M. Descrambles the program only during M1 fetches. Neither of Robert's boards has it - both use a PAL16L8 substitute.

PST518×1

Power-on reset generator. Holds the machine in reset until the supply is stable.