How a frame is drawn

Everything is one crystal

Sheet 5/8 is titled SYNCHRONOUS, and it means it literally: there is no second time domain anywhere in this machine. A 12MHz crystal oscillator built from plain inverters at 2N feeds a '74 divider at 2M, and every other clock is a division of that.

Six megahertz becomes the dot clock. Three megahertz clocks both Z80s. One and a half megahertz clocks both YM2203s. Nothing needs synchronising to anything else because nothing was ever separate.

The consequence is that the video timing is fixed by counting. The H counters at 2K and 1K run to 384 per line; the V counters at 2L and 1L run to 262 lines. Six million divided by 384 gives a line rate of 15.625kHz, and dividing that by 262 gives 59.64 frames per second. Nobody chose 59.64. It is what those two counter lengths produce, and MAME configures its screen with exactly the same pair of numbers.

One crystal, and everything else is a division of it. The whole machine is synchronous to a single 12MHz can: divide by two for the dot clock, by four for both processors, by eight for both sound chips. The frame rate is not designed, it is simply what falls out of 384 dots and 262 lines.

The counters are the screen

Those two counters are not merely keeping time, they are the coordinate system. The H count is the horizontal position and the V count is the scanline number, and both are distributed all over the machine as ordinary signals.

The sync sheet decodes a few specific counts into the pulses a monitor needs - horizontal sync, vertical sync, composite sync and the blanking intervals - but the counter outputs themselves travel much further. The V count addresses the interrupt PROM on the CPU sheet. It addresses another timing PROM on the sprite board. Its bottom bit swaps the sprite line buffers. It feeds the vertical scroll adders on the C board.

This is why the flip signal has to be handled so carefully across every sheet. Flipping the screen for a cocktail cabinet means inverting the counters, and every consumer needs the correctly flipped copy. Several of the naming traps in this model come from exactly that: boards making their own local inverted copies of shared timing.

The text layer, and time-slicing memory

Sheets 6/8 and 7/8 are the character layer: score, lives, the title screen, the mission text. It is a fixed grid of 8-by-8 tiles at D000 to D7FF, two bits per pixel, and it never scrolls.

The interesting part is not the graphics, it is the sharing. The CPU wants to write to this memory and the display needs to read it continuously, and they cannot both have it. So access alternates on H4 - a single bit of the horizontal counter. On one half of every group of eight pixels the display reads; on the other half the CPU may write.

That is the entire arbitration scheme: one address line from a counter that was already there, steering a set of multiplexers. No arbiter, no wait states, no request-and-grant. The CPU never even knows it is taking turns, because its window comes round faster than it can use it.

Sheet 7/8 turns the resulting tile number into pixels through the character ROM at 5D and a pair of '194 shifters, in the same load-eight-and-clock-them-out style the other two layers use.

Three layers arrive, one colour leaves

Sheet 8/8 is where the whole machine converges. Three pixel streams arrive every dot: characters from this board, sprites over the cable from the B board, background over the cable from the C board. One colour has to come out.

Each layer reserves one pen to mean transparent, and the depths differ: characters are 2 bits with pen 3 transparent, sprites 4 bits with pen 15, the background 3 bits and always opaque. The priority rule is a straight cascade - character, then sprite, then background - resolved by a few gates and a trio of '153 multiplexers. 3J, a '20, is the gate that spots a fully-set sprite pixel and declares it see-through.

The winner is a six-bit index, which is not enough on its own because all three layers would collide in the same palette. So a small PROM at 1H supplies the top bits, placing each layer in its own fixed range: background at 0 to 127, sprites at 128 to 191, characters at 192 to 255. MAME's palette handling splits the 256 entries the same way.

Then three more PROMs - 1D, 2D and 3D, one each for red, green and blue - turn that index into four bits per channel, and resistor ladders turn those into the analogue voltages the monitor wants. Twelve-bit colour, 4096 possible shades, 256 of them available at once. In MAME's ROM listing those three chips appear by name as vtb1.1d, vtb2.2d and vtb3.3d, tagged red, green and blue.

Three layers arrive at the colour mixer with different depths, and each has one pen reserved to mean "see through me". Text wins over sprites, sprites win over the background. The winning pixel indexes a 256-entry palette split into three fixed ranges, and three separate PROMs supply four bits each of red, green and blue.

Why so much of this is PROMs

Count them up and the video section leans on lookup tables constantly: interrupt timing, sprite-engine line timing, palette bank selection, and the three colour tables. That is not laziness, it is economics.

A bipolar PROM is a small, cheap, fast part whose contents cost nothing to change. Anything expressed as combinational logic needs gates, board space and a redesign if it turns out wrong. Anything expressed as a table needs one chip and a new burn.

So Capcom pushed every fixed decision they could into tables. Want the interrupt three lines later, the palette a shade warmer, the sprite buffers to swap at a different moment? Burn a different PROM and change nothing else. The board is, in a real sense, partly software.

The drawings behind this story

Each one opens the interactive schematic, where every chip and every net on the sheet can be traced pin by pin.

Every chip in this story

54 chips across 4 sheets. Click any of them to open the schematic with that chip selected. A few appear on more than one drawing, because Capcom split some packages across sheets.

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