Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Notes and open questions on this sheet (33)
Not yet walked against a physical board. The 343 pins and 101 nets on this sheet were read from the original drawing and cross-checked against MAME; every IC is still marked auto. Part numbers and pin assignments are what the drawing shows, not what has been metered.
Extraction uncertainty: 9N /CE pin is printed '23' where the other four ROMs print '20' in the same position (checked at 25x zoom). Almost certainly a hand-lettering slip for 20, but the sheet says 23.
Extraction uncertainty: 11L's symbol is lettered '68809' inside the body while the title block reads '68B09'.
Discrepancy vs IC index: 3C (74LS174), listed by the IC index as the ROM bank latch on this sheet, is NOT drawn anywhere on sheet 1/8. Every rectangular symbol on the page is otherwise accounted for. Its real home is unknown - check sheet 2/8 (MEMORY MAP / OUTPUT).
Discrepancy vs IC index: ROM capacities as drawn: 8N '128/256', 9N '128', 10N '128/256', 12N '128/256', 13N '128'. So 8N/10N/12N are jumper-selectable 27128-or-27256 and 9N/13N are 27128 only. The IC index claimed 13N is a 27256 - the drawing disagrees.
Discrepancy vs IC index: The 7K gate driving /WRAM is drawn De Morgan style: OR body with bubbles on BOTH inputs and the output, i.e. a true AND, consistent with 74LS08. Must not be recorded as an OR.
Discrepancy vs IC index: 7F: the designator is printed only beside the lower NAND; the upper NAND carries the part type '00' with no designator. Both are sections of the same package.
Discrepancy vs IC index: PST518 carries no reference designator on the drawing - only 'PST 518' beside the symbol.
Extraction uncertainty: RA5 and RA6 are drawn as ONE resistor symbol carrying BOTH designators stacked ('RA6' over 'RA5', caption '(22K x8 x2)'). There is no second symbol to box. I split that one symbol horizontally: RA6 gets the upper part (its own label + the pin-1 lead), RA5 the lower part (its own label + the zigzag). Neither box is a union of two symbols but the split line is mine, not the draughtsman's. The 'RA5'/'RA6' words that also appear over the address-bus lines to the left are annotations on the bus, not component symbols, so they are not boxed.
Extraction uncertainty: 11L is 48.3% of page HEIGHT (4.20% of page AREA). CONFIRMED LEGITIMATE: it is one single drawn rectangle for the MC68B09 DIP40, spanning almost the full height of the drawing, pin 7/VCC at the top down to GND at the bottom. Not a union.
Extraction uncertainty: 5N, 6N, 11H and 7L are each ~12-12.5% of page WIDTH, marginally over the 12% guide; each is one single drawn rectangle.
Extraction uncertainty: 11L pin 35 is lettered 'O' for Q; its wire runs straight up, crosses the ECLK branch with no junction dot, and stops at the top of the drawing with no label or destination. Coined $Q.
Extraction uncertainty: 11L's GND is drawn as a stub at the bottom of the box with no pin number printed (device VSS is pin 1).
Extraction uncertainty: A stray '12' is lettered on the E-clock wire between 11L pin 34 and 8K pin 6, at a small Z-jog with a short upward tick. Nothing is drawn above it and 8K's G1 is pin 6, so what the '12' refers to is unresolved.
Extraction uncertainty: 9J pin 3's label read as IRQ1; the final glyph could be 1 or I. No overbar visible.
Extraction uncertainty: /ROB (B22) and /AKB (B21): the final glyph is B-or-8 in this scan. Read as B, supported by the function (bus request / bus acknowledge).
Extraction uncertainty: BANK0's final glyph is 0-or-O.
Extraction uncertainty: 'to 2/6' on /EXTEN vs 'to 2/8' on /WRAM: 6-vs-8 lettering, recorded as read.
Extraction uncertainty: RA5 and RA6 common pin 1: the sheet marks the pin '1' and draws one representative 22K resistor, but the far end of that resistor is not legibly traceable at 400 DPI. Recorded as +5 by analogy with RA4, which does show +5 explicitly.
Extraction uncertainty: 5N pin 1 (DIR): the stub points at a nearby '+5' but the joining corner is not drawn. 6N's identical corner IS drawn, so 5N is recorded as +5.
Extraction uncertainty: 5N pin 19 and 6N pin 19 (/EN): drawn as short stubs with nothing on the end. Left as null rather than guessing GND.
Extraction uncertainty: 5K has no part number and no output pin number printed. Input pin 1 is confirmed; the output runs to 9L pin 10.
Extraction uncertainty: 5F, 8K and 7L carry no printed part number. 8K and 7L follow the '138 pinout exactly; 5F is a single inverter.
Extraction uncertainty: 8L and 7K each carry one printed "'08", lettered beside one gate of the group rather than on every gate.
Extraction uncertainty: The A13 / A14 / A15 verticals in the narrow channel just right of the CPU pin table run within a few pixels of one another and of the table's own box edge, so their junctions cannot be separated even at 5x. The assignments above were taken from the Capcom-printed A13 / A14 / A15 labels on each branch, which are unambiguous.
Discrepancy vs IC index: ROM data-pin numbering is shifted on the sheet: the shared data table prints 19,18,17,16,15,14,13,11 for D7..D0, i.e. 14 for D2 and 13 for D1 with 12 skipped. On a real 27128/27256 D2 is pin 13, D1 is pin 12 and pin 14 is GND. The same pin 14 is also (correctly) shown tied to ground in the VCC/VPP/OE/GND bracket, so pin 14 appears twice on every ROM. Recorded as printed on both rows.
Discrepancy vs IC index: 9N's chip-enable pin is printed 23 where 8N/10N/12N/13N print 20 for the same pin. Pin 23 is also the shared address table's A11 pin, so 9N shows 23 twice.
Discrepancy vs IC index: 8K's lower enables are printed 'G2A' (pin 4) and 'G1A' (pin 5); the device has G2A on 4 and G2B on 5. 7L prints the pair the other way round again, 'G2B' on pin 4 and 'G2A' on pin 5. Function is unaffected - 8K's pair is grounded and 7L's pair both take 8K output 2.
Discrepancy vs IC index: 8N and 9N both take A14 on pin 27. On a 27128 that pin is /PGM and must be high for reads, yet 9N covers 0x8000-0xBFFF where A14 = 0. Drawn as read; flagged because it matters if a real 27128 is fitted at 9N.
Discrepancy vs IC index: 8J draws the bubble on the input side for gates 9/8, 11/10 and 13/12 but on the output side for gate 5/6. Direction was taken from the '14 pinout (inputs are 9, 11, 13, 5) and is confirmed by 'to 2/8' on /ALC1, which makes pin 12 an output. 5F and 5K are likewise drawn bubble-on-input.
Discrepancy vs IC index: The 8L and 7K '08 gates and the 9L '32 gate are all drawn in De Morgan form with bubbles on both inputs and the output; only the body shape separates them. 8L/7K bodies are OR-shaped (a true AND, matching '08) and 9L's body is AND-shaped (a true OR, matching '32). Recorded by function with the part as printed.
Discrepancy vs IC index: 11L is lettered '68809' inside the body while the title block reads '68B09'.
BOARD FACT, confirmed by Robert against a factory Capcom board: the five ROM slots in column N are silkscreened 8N, 9N, 10N, 12N and 13N. Capcom's designators here are LABELS, not grid coordinates - the slot labelled 10N physically sits level with the 6809 at 11L, and 12N level with the sound CPU. On Robert's board 8N, 10N and 12N are fitted (27256, 27128, 27256) and 9N and 13N are empty. Three 32K and two 16K parts, 128K in total, which is the parent `gng` ROM set - and the board is confirmed to run it. The board-photo positions for these slots are pinned to their measured centres rather than derived from the grid, because the grid cannot express this.
