Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Notes and open questions on this sheet (21)
Not yet walked against a physical board. The 207 pins and 66 nets on this sheet were read from the original drawing and cross-checked against MAME; every IC is still marked auto. Part numbers and pin assignments are what the drawing shows, not what has been metered.
Extraction uncertainty: 1J pin 9 output label: two glyphs, the second is clearly 'B'; the first is an unreadable curl (could be 4, a Greek phi, or similar). Recorded as '?B'. The signal itself is unambiguous: it is 1J's buffer of 3K pin 8, i.e. 3 MHz = XTAL/4, and it leaves 'to 4/8'.
Extraction uncertainty: X6M vs 3K pin 6: the horizontal from 3K pin 6 (/1Q) is drawn crossing the X6M vertical with no junction dot, and both 3K pin 2 (D, the toggle feedback) and 3K pin 11 come from that X6M vertical. A toggle flip-flop requires D = /Q, so I have merged them: X6M = 3K pin 6. If Robert can bell-out 3K pin 6 to 1J pin 6 on the board that settles it.
Extraction uncertainty: 2J gate C (pins 9,10,11): pins 10 and 11 are bracketed together; I read them as V16 with pin 9 = V128, but the alternative (10/11 = V128, pin 9 = V16) is equally consistent with the ink. The gate function /(V16.V128) is the same either way. There is also an unexplained pin number '5' inked just above this gate's input bracket, next to the V16 line - I could not attach it to any chip (2J pin 5 is already used by the H1/XH2/XH4 gate near 2K).
Extraction uncertainty: The '08 AND gate drawn at (0.647,0.414) is lettered 3M, but 3M is also used for two 74LS74 halves. 4L only uses 3 of its 4 '08 gates, so this gate is very likely 4L pins 12/13/11 mis-lettered. Recorded as printed.
Extraction uncertainty: 3M ('74) pin 11 is drawn tied to pin 12 and to a ground symbol - i.e. the second flip-flop has D and CLK both grounded and is used purely as a /PRE - /CLR latch. The ground symbol is clear, but this is unusual enough to be worth a bench check.
Extraction uncertainty: L6M vs 16M: the label on 3K pin 5's net reads 'L6M'; the first character could be a letter L or a digit 1 (hand lettering). L6M reads better and matches X6M as a pair.
Extraction uncertainty: 5K pin 13's source: it taps a short horizontal that runs left from 1K's CA vertical at y=0.79, very close to (about 5 px above) the X6M bottom rail. I read it as 1K's carry, which makes /HINIT a once-per-line pulse - functionally the only sensible reading - but the two lines are nearly coincident in the scan.
Discrepancy vs IC index: CLOCK TREE (positive finding, agrees with MAME on XTAL/2 and XTAL/4). XL is a 12 MHz crystal in a two-inverter oscillator built from 3N gates 9->8 and 1->2, with R45 220R and R43 220R as the bias resistors, C13 101 and C12 104 as the coupling caps, R44 680R and R46 to ground. 3N 13->12 buffers the oscillator to $12M. 3K (74LS74) does ALL of the division on this sheet: half A toggles on 12 MHz giving 6 MHz (Q = L6M, /Q = X6M = XTAL/2), half B toggles on X6M giving 3 MHz (Q = H1, /Q buffered by 1J pin 9 out to sheet 4/8 = XTAL/4). MAME's '6809 at XTAL/2' matches the 6M that leaves on CN-2 C3 and 'to 7/8'; MAME's 'sound Z80 at XTAL/4' matches the 3 MHz on 1J pin 9 going 'to 4/8'.
Discrepancy vs IC index: NO XTAL/8 IS PRODUCED HERE. There is no divide-by-8 anywhere on 85606-A-2-5/8, so MAME's 'both YM2203 at XTAL/8' must be generated on another sheet (most likely by dividing the 3 MHz that leaves on 1J pin 9). Likewise nothing on this sheet makes a 1.5 MHz E clock; the 6809's E/Q come from the CPU itself given 6M.
Discrepancy vs IC index: H COUNTER = 384 (positive finding, matches MAME htotal 384 and hbend 128). The chain is H1 (3K half B, 3 MHz) + 2K (H2,H4,H8,H16) + 1K (H32,H64,H128,H256). 2K and 1K are clocked by X6M and count-enabled by H1 (P=T=H1 on 2K, P=T=2K's RCO on 1K), so the 8-bit field H2..H256 advances once every two 6 MHz clocks. Preset wiring: 2K A,B,C,D all grounded; 1K A=GND, B bracketed to A, C=+5, D=GND. That reloads the 8-bit field with 64, i.e. the 9-bit H value H1..H256 restarts at 128 - exactly MAME's hbend=128. Counting 64..255 is 192 states, times 2 for H1, = 384 clocks of 6 MHz per line = 15.625 kHz. Reload is 1K pin 15 (RCO) -> 5K pin 11 -> 5K pin 10 -> /LOAD of both counters.
Discrepancy vs IC index: V COUNTER = 272 LINES ON THE DRAWING, NOT 262 (discrepancy with MAME). 3L half A samples 1K's RCO on X6M to make VCLK, one 6 MHz-wide pulse per line; 3L half B toggles on VCLK to make V1. 1L and 2L are clocked by VCLK and count-enabled by V1 (P=T=V1 on 1L, P=T=1L's RCO on 2L), so the 8-bit field V2..V256 advances every second line. Preset wiring read pixel by pixel: 1L pins 3,4,5 bracketed to GND and pin 6 to +5 (nibble 1000, V16=1); 2L pins 3,4,5 bracketed to +5 and pin 6 to GND (nibble 0111, V32/V64/V128=1). That is a reload value of 120, so the field runs 120..255 = 136 states, times 2 lines = 272 lines per frame. Reload is 2L pin 15 (RCO) -> 3N pin 11 -> 3N pin 10 -> /LOAD of 1L and 2L. 272 lines gives 15.625 kHz / 272 = 57.4 Hz, whereas MAME's 262 gives 59.6 Hz. I could not find any second reload path that would shorten the frame to 262. Worth a scope check of the frame rate on the real board.
Discrepancy vs IC index: VISIBLE LINES = 224 (positive finding, matches MAME vbend 22 / vbstart 246). Vertical blanking is an S-R latch: 3M's second '74 half has D and CLK grounded and is driven only by /PRE and /CLR. 1M (74LS30, three inputs tied high) NANDs V16.V32.V64.V128.V256 into /PRE, so blanking starts when the 9-bit V value reaches 496. 2J gate C NANDs V16 with V128, and 2J gate A NANDs V16, that result and V256 into /CLR, so blanking ends at V=272. With the counter running 240..511 that is 16 + 32 = 48 blanked lines out of 272, leaving exactly 224 active lines - the same active height MAME uses.
Discrepancy vs IC index: HORIZONTAL BLANKING. 2J gate B NANDs H1, XH2 and XH4; 5K 5->6 re-inverts it; 5L gates it with H256 (gate 12/13 with /H256 -> J, gate 9/10 with H256 -> K) into 5M, a 74LS112 JK flip-flop clocked by L6M. 5M /Q (pin 6) is LHBL, out to CN-2 D9 and sheet 8/8. LHBL therefore changes state only on an H&7==7 boundary: it asserts at H=135 and releases at H=263, a 128-count blanking window with 256 counts active - the same 256/128 split MAME expresses as htotal 384 with hbend 128 and hbstart 0.
Discrepancy vs IC index: HORIZONTAL SYNC. 4K (74LS138) takes A=H16, B=H32, C=H64, G1=+5, /G2A=H256, /G2B=GND, so it only decodes while H256 is low. Its Y3 (pin 12) and Y4 (pin 11) go to the 3M-lettered 74LS08 gate, which is drawn with bubbles on BOTH inputs - the De Morgan dual, i.e. its output is low when either decode is selected. That covers counts 176..207, a 32-count / 5.33 us horizontal sync pulse.
Discrepancy vs IC index: VERTICAL SYNC AND COMPOSITE SYNC. 2M (74LS138) takes A=V8, B=V128, C=V256, G1=+5, /G2B=GND and /G2A from the vertical-blank latch, so it only decodes during vertical blanking; Y3 (pin 12) is vertical sync. The 4L 74LS08 gate at pins 4,5 -> 6 is again drawn with bubbles on both inputs and ORs the two active-low syncs; its output goes through R40 220R to the connector pin lettered F, marked CMP SYNC. So composite sync is active-low and is the OR of the H and V sync pulses.
Discrepancy vs IC index: PIXEL-PHASE STROBES. The four '4N' 74LS74 halves re-time the H&7 decode: one pair clocked by L6M and X6M produces OH on the second half's /Q (CN-2 D3, 'to 6/8'), the other pair produces 4-3H on the first half's Q (CN-2 C4, 'to 7/8') and 4H on the second half's Q (CN-2 D4, 'to 6/8' and 'to 7/8'). 4L 9,10->8 (H1.XH2) is the D of the 4-3H stage and 4L 1,2->3 ((4-3H)./XH4) is the D of the 4H stage.
Discrepancy vs IC index: IRQ AND HINIT. 3M's latch Q (pin 9) leaves the sheet as IRQ1 'to 1/8', so the main CPU interrupt is exactly the vertical blanking window. 1K's carry is inverted a SECOND time by 5K 13->12 to give /HINIT (overbar printed) on CN-2 C18 - a distinct net from the /LOAD produced by 5K 11->10, even though both invert the same input. Do not merge them.
Discrepancy vs IC index: NAMING: the brief asked about V1F..V128F and OB. Neither appears on this sheet. The vertical taps are plain V1..V256 and there is no 'F' suffix anywhere. 'OB' is almost certainly a misreading of OH, the pixel strobe on CN-2 D3. V256 never leaves the sheet - it is used only by 2M, 1M and 2J.
Discrepancy vs IC index: COUNTER BIT EXITS: H1..H256 all leave on CN-2 C5/D5/C6/D6/C7/D7/C8/D8/C9 and H8..H128 additionally go 'to 6/8'; H2 goes 'to 6/8' and H4 and 6M 'to 7/8' through the 1J buffer. V1..V128 leave on CN-2 C10..D13, with V1..V4 'to 7/8', V8..V128 'to 6/8' and V32 also 'to 4/8'. LHBL leaves on CN-2 D9 and 'to 8/8'; LVBL leaves only as 'to 8/8' (no CN-2 pin on this sheet).
Discrepancy vs IC index: TWO SHARED DESIGNATORS ON THIS SHEET. The drawing letters two separate 74LS74 packages as 4N, and gives the ref 3M to both a '74 and an '08 gate. Modelled as 4N/4N(b) and 3M/3M(gate) so each physical package exists once. Same class of fault as the duplicated 4E on sheet 8/8.
