Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Notes and open questions on this sheet (12)
Not yet walked against a physical board. The 205 pins and 107 nets on this sheet were read from the original drawing and cross-checked against MAME; every IC is still marked auto. Part numbers and pin assignments are what the drawing shows, not what has been metered.
Extraction uncertainty: item: OH (8F pin 9 clock, 'from 5/8'); issue: first glyph is a rounded O; cannot tell letter O from digit 0 in this hand lettering. Could be '0H'. Recorded as printed: OH.; confidence: medium
Extraction uncertainty: item: CHHFLIPa (8F pin 10); issue: trailing character is a small subscript; could be Latin 'a' or Greek alpha. Recorded as printed with a plain 'a'.; confidence: medium
Extraction uncertainty: item: H4/H2 vs 4H; issue: the sheet uses BOTH spellings. 'H4' and 'H2' arrive on the left in the same 'from 5/8' bracket as V128..V8/H128..H8; '4H from 5/8' and 'OH from 5/8' arrive separately on the right. They are drawn as different labels and are NOT joined anywhere on this sheet, so they are recorded as distinct nets. Functionally 4H behaves exactly like H4 (8H must latch the attribute at the H4 0->1 edge), so they may be the same node or a buffered copy. Needs sheet 5/8 to settle.; confidence: high that they are drawn separately; low on whether they are electrically one net
Extraction uncertainty: item: 5F and 5K part numbers; issue: no part number is printed next to either inverter. Their pin pairs (11->10 and 3->4) match 74LS04 sections, but that is inference, not the drawing.; confidence: part not stated
Extraction uncertainty: item: 7H pin 18 'CE'; issue: printed without a visible overbar although pin 20 'OE' clearly has one. Recorded as printed. It is grounded either way.; confidence: high on the reading, the bar genuinely is absent
Extraction uncertainty: item: AB8 / AB0 / DB0 / DC0 / AC0 / CC0 zeros; issue: hand-lettered 0 and O are near identical throughout; read as digits from bus context.; confidence: high
Discrepancy vs IC index: item: FLIP printed on both sides of the 5J buffer; detail: The signal arriving 'from 2/8' is labelled FLIP and drives 5J pin 4 (pin 5 grounded, so the section is a non-inverting buffer). The pin-group box that feeds 3J/4J pins 2,5,10,13 and 5J pins 10,13 is ALSO labelled FLIP. Per the derived-copy rule these are two different nets; a naive netlist merge would short 5J pin 4 to pin 6. Both are recorded as 'FLIP' because that is what is printed - the model must board-scope or suffix one of them before merging with other sheets.
Discrepancy vs IC index: item: Crossing convention is not uniform; detail: Most 4-way crossings on this sheet break the vertical with a visible white gap (e.g. the SEL column crossing H2, the 5F input crossing the '245 /EN line, DC7 crossing the two long verticals). But the /CHARCS column at x=0.318 runs unbroken straight through the 6F pin-12 horizontal at y=0.809, which is a genuine T/4-way CONNECTION - it is the only thing that drives 6F pins 5 and 12, and the resulting logic (write strobe = RDB OR /CHARCS; wait = /CHARCS AND NOT(H2*H4)) is exactly right. Verified at pixel level; a reader who assumes 'crossing = no connect' everywhere will leave two gate inputs undriven.
Discrepancy vs IC index: item: '157 stack is drawn twice; detail: 3H/4H/5H each appear as two rectangles: an A-input stack top-left ('(A)' marker next to 4H) and a B-input/Y-output stack in the centre ('(B) (Y)' marker next to 4H). Same three physical packages, two boxes each.
Discrepancy vs IC index: item: The 12-wire ordinal column; detail: The numbers 12,11,10...1 printed INSIDE the '157 boxes are cable ordinals, not pin numbers and not channel numbers. The real pin numbers are printed outside the boxes on every lead. Ordinal 12 is the /WE channel, ordinals 11..1 are RAM A10..A0.
Discrepancy vs IC index: FLIP is printed on both sides of the 5J buffer (pin 4 in, pin 6 out, pin 5 grounded). The output is modelled as $FLIPBUF so the two do not false-join. Which of the XOR packs consume the buffered copy versus the incoming rail is NOT settled by the drawing.
