Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Notes and open questions on this sheet (15)
Not yet walked against a physical board. The 299 pins and 128 nets on this sheet were read from the original drawing and cross-checked against MAME; every IC is still marked auto. Part numbers and pin assignments are what the drawing shows, not what has been metered.
Extraction uncertainty: The eight wires entering the top edge that carry the CPU palette write data each have a single-character overbarred label that could not be resolved at 400 DPI - every one looks like an oval with a broken bar above it. Coined $PD3-$PD0 and $PG3-$PG0. Real names need a better scan.
Extraction uncertainty: The palette address bus is labelled on the drawing only with bare digits 7..0. Scoped here as $PALA7-$PALA0 so the digits cannot false-join anything else.
Extraction uncertainty: 4D's CLK and /CL sources are not resolved - both stubs join a horizontal that merges with the 6D/7D write-strobe vertical. Coined $4DCK and $4DCL.
Extraction uncertainty: 6E pin 5 and 7E pin 6 run into a congested area and could not be followed to their loads. They are the obvious sources for the '367 enables and the palette write strobes, but that is not verified, so $VEN1/$VEN2/$PWERG/$PWEB are coined and unsourced.
Extraction uncertainty: The '153 Y-to-4D mapping is read from the non-crossing staircase order of the wires rather than by following each wire individually.
Extraction uncertainty: 5F has no part number printed; 74LS04 is inferred from the symbol, not asserted by the drawing.
Discrepancy vs IC index: THE 4E DUPLICATION IS REAL, NOT A MIS-READ. Cropped at 14x: a 74LS174 hex latch is marked 4E, and a 74LS153 dual mux is marked 4E in all three of its drawn blocks. Both E glyphs have a fully formed bottom stroke - neither is an F. The mux family runs 3F/3E/4E and the sheet note '153 x 3' backs that up, so the error is most likely on the '174 (probably 4F), but the drawing does not say so and the board must settle it. Recorded here as 4E and 4E(mux).
Discrepancy vs IC index: THE PALETTE IS RAM, CONFIRMED FROM THE SILICON: 6D red, 7D green, 8D blue, each with A8/A9//CE grounded giving exactly 256 entries. 6D and 7D share a write strobe while 8D has its own, and the CPU-side buffer enables split the same way (/RGCS for red+green, /BCS for blue) - which confirms MAME's two-address-range palette map from the other direction.
Discrepancy vs IC index: Commando's three colour PROMs are gone, but a PROM survives here in a completely different role: the unlabelled 256x4 is the LAYER-PRIORITY lookup, not a palette. Its two outputs are both the '153 mux select and the top two palette address bits, so the priority decision also chooses the palette bank.
Discrepancy vs IC index: Layer select decodes as B:A = 00 background, 01 sprite, 10 or 11 character. Only three layers are selectable because C3 and C2 are strapped together to the CHAR bit on all six muxes.
Discrepancy vs IC index: All six '153 strobe pins are bussed together and grounded - the muxes are never disabled. The drawn labels /6ST../1ST are PIN names, not net names.
Discrepancy vs IC index: Transparency detection: 7F NANDs CHARA and CHARB (character pen 3), 1F NANDs all four OBJ bits (sprite pen 15). Both drawn as De Morgan duals with bubbled inputs and no output bubble.
Extraction uncertainty: 5C ('245) is 11.3% of page WIDTH - one single drawn rectangle, drawn wide because it is the only horizontally-oriented '245 on the sheet.
Extraction uncertainty: The '2148H x3' type caption sits above the 6D cell and is included in 6D's box; the '153 x 3' caption at the foot of the mux stack belongs to all nine sections and is in none of them.
