Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Notes and open questions on this sheet (27)
Not yet walked against a physical board. The 155 pins and 61 nets on this sheet were read from the original drawing and cross-checked against MAME; every IC is still marked auto. Part numbers and pin assignments are what the drawing shows, not what has been metered.
Extraction uncertainty: Net label at 'from 1/9' just below H1 reads as a lollipop/Greek glyph followed by two characters that are either BB or 88 - most likely a phi. Recorded as the coined net $CTRCLK. Needs a call on the glyph.
Extraction uncertainty: That same label sits on a node that is unambiguously driven by 8D pin 12 (a solid, unbroken cross at x=787,y=1417 in the 4678x3306 scan). So either the 'from' annotation is a drafting slip and the net is generated here and exported to 1/9, or the same clock is regenerated on both sheets. Flagged, not resolved.
Extraction uncertainty: 'AKB' (from 1/9, barred): third character could be B or 8.
Extraction uncertainty: 'LVI' (from 4/9): last character could be I or 1. Recorded as LV1 by analogy with the sister board, but the glyph is ambiguous.
Extraction uncertainty: 'OB' bus digits and 'OBA' digits: the drawing's 8 and B are near-identical; OB8 vs OBB was resolved from the bus label 'OB8~OB0 to 1/9' at the top right.
Extraction uncertainty: The inverters drawn 13->12 (12D, 8D, 6H) carry the bubble on the INPUT side, while the 5E inverters and the 8D 11->10 section carry it on the output. Direction was taken from the 74LS04 pinout (odd pins in, even pins out), not from the bubble.
Extraction uncertainty: 1J pin 4 and 1J pin 10 sources not traced to their driver (pin 2 = 6E CA, traced).
Extraction uncertainty: 2H pin 1, 2H pin 2 and 2H pin 5 sources not traced to their driver (pin 9 = 6E CA, traced). 2H pin 6 output runs left off the traced region.
Extraction uncertainty: 3H pin 4 source: it is a long horizontal at y~1682 running right past several hop-overs; endpoint not resolved. 3H pin 13 source is a vertical at x~2642 dropping from above; endpoint not resolved.
Extraction uncertainty: 6F pins 4 and 5 (second gate) sources not traced.
Extraction uncertainty: 5F pin 6 output runs left off the traced region.
Extraction uncertainty: 5H pin 7/10 ($OBAEN) is a T onto the same horizontal that feeds 5F pin 5; the driver of that horizontal lies further right and was not resolved.
Extraction uncertainty: 4H pin 2 CLK: its wire runs left and disappears behind the 5H symbol at x~2992. Taken as the same $CTRCLK net as 5H pin 2 on the strength of the synchronous cascade, but not visually continuous.
Extraction uncertainty: VCC/GND pins (16/8 on the '161s and '74, 14/7 on the gate packages) are not drawn on the sheet and are omitted.
Discrepancy vs IC index: *** /OVER96 IS GENERATED BY 5F (74LS00) PINS 1,2 -> 3. Pin 1 = OB7, pin 2 = OB8, output pin 3 carries the label OVER96 WITH A CLEAR OVERBAR, annotated 'to 1/9'. That is the whole of it: /OVER96 = NAND(OB7, OB8). Both input horizontals were followed pixel by pixel to solid junctions on the OB7 and OB8 verticals (which descend from 7D pins 13 and 12).
Discrepancy vs IC index: *** WHY THAT MAKES 96. OB0 and OB1 (from 6E QA/QB) are the byte-within-record address; OB2..OB8 (6D QA-QD then 7D QA-QC) are the 7-bit record number, matching the 128-record / 512-byte object RAM on sheet 1/9. Record 96 is 1100000b, i.e. OB8=1 and OB7=1 and nothing else. NAND(OB7,OB8) therefore goes low exactly at record 96 and stays low for 96..127, so /OVER96 asserts on the first record past the 96th and is what stops the scan.
Discrepancy vs IC index: *** THE 96 COUNTER IS NOT PRESET AT ALL. All four data inputs of 6D and all four of 7D are hard-grounded (the drawing ties pins 3,4,5,6 together with a bar and takes pin 3 to a ground symbol on both chips). So the record counter loads ZERO, counts up from 0, and the ceiling comes purely from decoding OB7 and OB8. This is NOT the Commando 'preload 8, run to 31' trick - the object-list counter here is a plain 0..95 run terminated by a decode.
Discrepancy vs IC index: *** THE PER-LINE CEILING OF 24 *IS* THE COMMANDO TRICK, AND IT LIVES IN 5H/4H. 5H's preset wiring is A, B and C strapped together to ground and D strapped to +5 = binary 01000 = 8; 4H's four data inputs are all grounded. So the 5-bit slot address OBA0..OBA4 (5H QA-QD = OBA0..OBA3, 4H QA = OBA4) loads 8 and counts 8,9,...,31 = EXACTLY 24 SLOTS, the same as Commando.
Discrepancy vs IC index: *** THE 24 LIMIT IS ENFORCED BY 4H QB VIA 5E. 4H QB (pin 13) is bit 5 of the slot counter - it can only set when the count rolls past 31 to 32. It goes to 5E (74LS04) pin 9 and comes out inverted on pin 8 as the barred net /OVER24. So /OVER24 falls the instant the 24th slot has been filled. QC, QD and CA of 4H are unconnected; QB exists solely to be the overflow flag.
Discrepancy vs IC index: *** WHERE /OVER24 GOES. Two places, both traced to solid junctions: 6E pin 1 (/CL - it clears the byte-within-record counter) and 1H pin 4 (one input of the 74LS20 whose output is /OBJABWR, the object-buffer write strobe sent to 3/9). So when 24 slots are full the write strobe is inhibited and the byte counter is held clear.
Discrepancy vs IC index: *** THE LOAD-TO-8 IS DRIVEN BY 3H PINS 1,2 -> 3, which goes to /LD of BOTH 5H and 4H (5H pin 9 and 4H pin 9 are the same net; 4H's wire runs down and left to join 5H's). 3H pin 1 is /HINIT (barred, from the pin-18 connector at the bottom of the sheet) and pin 2 is 2J /Q. So the slot counter is reloaded to 8 at horizontal init / at the start of each 24/96 phase.
Discrepancy vs IC index: The equivalent reload for the 96-record counter is 3H pins 12,13 -> 11, which drives /LD of both 6D and 7D (traced through a solid cross at x=2890,y=1596). Since their data inputs are grounded, that load resets the record number to 0.
Discrepancy vs IC index: All five '161 counters and inverter 6H share one clock, produced by 8D pin 12 inverting H1 from sheet 3/9. Confirmed by following the horizontal from y~1417 across to 6D pin 2 and 7D pin 2 and down the vertical at x~2191 to 5H pin 2 and 6H pin 13.
Discrepancy vs IC index: 6E's preload is the odd one on this sheet: A grounded, B from 8D pin 10, C and D tied together and taken from 6F pin 6. With 6F pin 6 high the preload value is 1100b = 12 (so 6E runs 12..15, four states, one per byte of a record, and its carry steps 6D once per record); with 6F pin 6 low the preload is 0010b = 2. That two-way preset is what switches between reading one byte per object and reading all four.
Discrepancy vs IC index: 6F pins 1,13,2 -> 12 decodes OB6 AND OB8 AND the 6D carry = record 95 (the last valid record), and 5F pins 12,13 -> 11 combines it with /OVER96. That output runs down and left into 5F pin 4. So the sheet has both a 'last record' term and an 'over 96' term.
Discrepancy vs IC index: Every gate on this sheet except 3D is drawn in De Morgan form with the signal flowing right to left. The '32 packages appear as AND bodies with bubbles on inputs and output; the '08 packages appear as OR bodies with bubbles on inputs and output; the '00 and '10 packages appear as AND/OR bodies with bubbles on the inputs only. Parts are recorded as printed.
