Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Notes and open questions on this sheet (16)
Not yet walked against a physical board. The 344 pins and 151 nets on this sheet were read from the original drawing and cross-checked against MAME; every IC is still marked auto. Part numbers and pin assignments are what the drawing shows, not what has been metered.
Extraction uncertainty: Greek suffixes: the Y latch outputs read Va7-Va0 and the adder results LVb7-LVb4 / Vb3-Vb0. The suffix is a small looped character, almost certainly alpha and beta as on the sister board, but it could be a lowercase a/b.
Extraction uncertainty: 9H/9J pin 1 reads LVI or LV1 - the third glyph is a bare vertical stroke.
Extraction uncertainty: 9H/9J pin 15 reads 24/96TM; the T could be an I or a 1, and no overbar is separable from the label-box border.
Extraction uncertainty: The SEL//ST assignment comes from the y-alignment of the two wire stubs against the two stacked label boxes; the stubs stop a few pixels short, so the pairing is inferred.
Extraction uncertainty: 8E and 7E share a clock rail whose printed label sits in the top margin and is sliced off by the page edge - only character bottoms survive. Coined $V175CLK rather than guess.
Extraction uncertainty: VIN ZONE is lettered on two lines; recorded as one net name with a space.
Discrepancy vs IC index: THE ROW ARITHMETIC IS A SUBTRACTER, NOT AN ADDER. 8E and 7E feed the adders from their /Q outputs only, and 7F has C0 tied to ground with A1 tied to +5. That makes stage A a two's-complement negate of V, so the '283 chain subtracts. This confirms the row-arithmetic hypothesis from the silicon.
Discrepancy vs IC index: 6J AND 5J ARE CASCADED, not latching different bytes in parallel: 6J's Q feeds 5J's D, and 5J re-latches one byte-slot later.
Discrepancy vs IC index: 9K's byte decode lines up with MAME's record layout exactly: Y0 clocks the code byte, Y1 the attributes, Y2 (/TR2) opens the Y latch, Y3 gates with H1 to make /TR1 for the off-sheet X latch. Attribute bits map DF0 to HOVER (X bit 8), DF2 to OBVFLIP, DF3 to OBHFLIP, DF4/DF5 to COL4/COL5, DF6/DF7 to AD8/AD9.
Discrepancy vs IC index: H8 IS DELIBERATELY SKIPPED in the store address (H2, H4, H16, H32, H64, H128, H256), so the byte-within-record bits advance every 4 pixels. The same hole appears in both banks.
Discrepancy vs IC index: MIXED '157 CONVENTIONS ON ONE SHEET: the 13H/14H and 13J/14J blocks number their bus lines 1-8 top to bottom, reversed against the datasheet, while the 9H/9J block runs the datasheet way. All pin numbers are transcribed as printed - do not normalise them.
Discrepancy vs IC index: 5D's second XOR takes its pin-10 input from 5D pin 11 (OBH4), not from the flip signal. Checked at 13x: the output wire runs right, the corner rises to the OBH4 label, and the same node continues to pin 10. So OBH8 = OBH4 XOR H8, not the plain flip-XOR you would expect.
Discrepancy vs IC index: 8J pin 5 (Q2, from attribute bit 1) is not drawn - consistent with that bit being unused.
Discrepancy vs IC index: 13H/14H, 13J/14J and 9H/9J are drawn as merged two-chip blocks with the designator appearing twice in each block, so those boxes are per-chip unions and overlap their partner.
Extraction uncertainty: 6H: only 5 of the six 74LS04 inverter sections are drawn on this sheet (pins 1/2, 3/4, 5/6, 9/8, 11/10). The 13/12 section does not appear here.
