Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Notes and open questions on this sheet (14)
Not yet walked against a physical board. The 192 pins and 80 nets on this sheet were read from the original drawing and cross-checked against MAME; every IC is still marked auto. Part numbers and pin assignments are what the drawing shows, not what has been metered.
Extraction uncertainty: 'LV1a' third glyph is I vs 1 and the suffix a vs Greek alpha; recorded /LV1a. The overbar is clearly present.
Extraction uncertainty: 13M's Q-output pin numbers are NOT printed; 2/5/6/9/12/15/16/19 are inferred from the '273's D-to-Q pairing rather than read.
Extraction uncertainty: The (A)/(B) group pin numbers on 12L/13L and 14M/14N are not printed for both groups; the missing set is inferred from Capcom's printed top-to-bottom channel order on the sibling.
Extraction uncertainty: RA4's common pin is inferred as 1. RA7 and the CN-2 array have no pin numbers printed at all.
Extraction uncertainty: A small '1' glyph sits on the 10N pin-3 wire between the DF and /1LOAD lines; purpose unknown, topology unaffected.
Extraction uncertainty: /1ST carries no 'from x/9' annotation, so its off-sheet source is not stated here.
Discrepancy vs IC index: 12N (CXK5808P, 22-pin) and 13N (TMM2018, 24-pin) are wired to IDENTICAL nets. 13N is drawn dashed and its left-side leads are stubs reaching no wire: it is an ALTERNATIVE FOOTPRINT for the same 256-byte buffer, not a second RAM. The IC index counts both as chips.
Discrepancy vs IC index: PRIORITY POLARITY DIFFERS FROM THE SISTER BOARD. Commando tested emptiness with a '20 NAND; here 14L is a '21 AND over the LOW NIBBLE ONLY (OBJI0-3), active high, driving the printed net SEL straight into the mux selects. Same first-sprite-wins outcome, opposite polarity - must not be copied across from the older model.
Discrepancy vs IC index: The ninth X bit (10N QA) is NOT XORed with OBFLIP1 the way bits 0-7 are. It goes straight to the RAM /CE, which is what makes right-edge clipping free.
Discrepancy vs IC index: Capcom's (A)/(B) group letters on the '257s are the REVERSE of the datasheet: the sheet's '(A)' is pins 13/10/6/3 (datasheet B inputs) and '(B)' is pins 14/11/5/2 (datasheet A). Channels run 1-4 top to bottom, matching the known quirk from the sister project.
Extraction uncertainty: 13N is drawn dashed (alternative TMM2018 footprint); boxed where drawn
Extraction uncertainty: 12L/13L and 14M/14N each drawn in two sections (B-input section and A/Y-output section); one box per section
Extraction uncertainty: 12M/11M each given four boxes, one per XOR gate; the package designator sits with the first (12M) / last (11M) gate
