Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Notes and open questions on this sheet (15)
Not yet walked against a physical board. The 164 pins and 62 nets on this sheet were read from the original drawing and cross-checked against MAME; every IC is still marked auto. Part numbers and pin assignments are what the drawing shows, not what has been metered.
Extraction uncertainty: item: 74LS257 (B)-side input pin numbers on 6L and 7L; detail: Capcom prints only the channel index (1,2,3,4 for 6L; 5,6,7,8 for 7L) beside OBJ27..OBJ20 in the (B) block; no DIP pin numbers appear there. The pin numbers 14/11/5/2 given above are DERIVED from the printed (A)/(Y) pin numbers on the same chips (13/10/6/3 in, 12/9/7/4 out), which fix Capcom channel index 1..4 = datasheet channel 4..1. Worth walking on the board before it is treated as read.
Extraction uncertainty: item: 74LS273 Q-output pin numbers; detail: The Q side of the '273 shows only '(Q)' and the net names OBJ27..OBJ20; no pin numbers are printed (same on 5/9). 19/16/15/12/9/6/5/2 above is the datasheet order matched to the printed D-side order 18/17/14/13/8/7/4/3.
Extraction uncertainty: item: L6M8 - last character; detail: Reads as an '8' (two clear lobes) rather than Capcom's slashed zero, but 8 vs 0 on a clock name is exactly the trap CLAUDE.md warns about. Recorded as printed: L6M8.
Extraction uncertainty: item: 8N part number TMM2108 vs TMM2018; detail: The glyph order on 6/9 is unambiguously T M M 2 1 0 8; on 5/9 the same footprint is unambiguously T M M 2 0 1 8. Toshiba's real 24-pin 2K x 8 SRAM is the TMM2018, so 6/9 almost certainly carries a transposition, but it is recorded here as printed.
Extraction uncertainty: item: 14L gate outline; detail: The '21 is drawn mirrored (output at the left). The outline has a pointed output end and the input edge carries an extra inward arc, so on shape alone it reads more like an OR than an AND. There are NO bubbles anywhere on the gate. The part is printed '21 and the identical outline is used for the same function on 5/9, so it is recorded as a 74LS21 four-input AND, per the printed part.
Extraction uncertainty: item: OBFLIP2; detail: Printed with a visible space, 'OBFLIP 2'. No overbar. Recorded as OBFLIP2.
Discrepancy vs IC index: THE '273 HAS NO REFERENCE DESIGNATOR. The box interior is genuinely blank above '(D) (Q)' - checked at 12x with contrast stretched. The equivalent latch on 5/9 is printed 13M. Do not guess 6M; the drawing does not say.
Discrepancy vs IC index: The brief's expectation was wrong: the '257 output muxes and the transparency test are NOT shared with 5/9. This sheet has its own '257 pair (6L, 7L) and its own transparency AND. What is genuinely shared is the '21 PACKAGE 14L (one gate per sheet) and the final output stage: 5/9 carries a second '257 pair (14M, 14N) plus the CN-2 connector, and this sheet has no counterpart - it simply exports 'OBJ27 ~ OBJ20 to 5/9'.
Discrepancy vs IC index: 5/9 carries a pull-up array RA4 (1K x 8) on the COL0..COL7 lines. 6/9 has NO equivalent array on its COL inputs - the COL bus is pulled up once, on 5/9. The only array here is RA6 on the internal data bus (RA7 plays that role on 5/9).
Discrepancy vs IC index: Capcom's (A)/(B) group letters on the '257s are the REVERSE of the datasheet, exactly as on 5/9: the group Capcom calls '(A)' takes pins 13/10/6/3, which are the datasheet's B inputs, and its outputs are pins 12/9/7/4 (the datasheet's Y). Capcom's channel index runs 1..4 top to bottom = datasheet channel 4..1. THIS SHEET USES THAT REVERSED CONVENTION THROUGHOUT.
Discrepancy vs IC index: 7N and 8N are alternative footprints for one physical RAM (8N is drawn dashed), same as 12N/13N on 5/9. But the wiring is drawn asymmetrically: 8N's whole left side (A0..A7, /CE) is floating stubs labelled only with pin numbers, while 7N's /WE (pin 17) is the stub and 8N's /WE (pin 21) carries the only real wire to /2WR. Both /WE pins are the same net.
Discrepancy vs IC index: Sheet 6/9 uses a 9-bit counter identical in structure to 5/9 (9L/9M/9N here vs 10L/10M/10N there), same DF7~DF0 + HOVER load, same bit-8-to-/CE trick. The XOR pair is 7M/8M here vs 12M/11M on 5/9, and the flip control is OBFLIP2 rather than OBFLIP1.
Discrepancy vs IC index: All the per-buffer control signals are '2'-prefixed copies of 5/9's '1'-prefixed ones: /2ST, /2LOAD, /2WR, /2CL against /1ST, /1LOAD, /1WR, /1CL. OB6M, HOVER, DF7~DF0, COL7..COL0 and L6M8 are shared, unnumbered names common to both sheets - do not board-scope those.
Discrepancy vs IC index: SEL is printed on both 5/9 and 6/9 but driven by different gates of the shared 14L '21. Modelled here as $SEL2 so the two cannot false-join; the printed name is kept on each pin.
