Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Notes and open questions on this sheet (17)
Not yet walked against a physical board. The 160 pins and 84 nets on this sheet were read from the original drawing and cross-checked against MAME; every IC is still marked auto. Part numbers and pin assignments are what the drawing shows, not what has been metered.
Extraction uncertainty: 14C pin 9 input glyph is ambiguous between H6 and H8; read as H8 only because the eight labels run H128 H64 H32 H16 ? H4 H2 H1.
Extraction uncertainty: SOH (8C pin 3): the middle glyph is a wide round O and may well be S0H with a zero. S7H/S4H/S2H are unambiguously digits.
Extraction uncertainty: FLIPa: the suffix is a small subscript glyph, 'a' or Greek alpha.
Extraction uncertainty: The connector bubble on /SCRCS reads B1 plus a smudged third character, most likely B14. /CBCS is clearly B13 and /MRDY2 clearly B15.
Extraction uncertainty: 14A CL pin number is not printed; the stub goes to +5 and pin 1 is assumed from the 74LS74 pinout rather than read off the drawing.
Discrepancy vs IC index: FLIP NAME COLLISION: the sheet input at 12D pin 3 is printed FLIP, and 12D pin 6 - two inversions later - is printed FLIP again. These are two physically distinct nets and must not be merged. Everything on this sheet that consumes FLIP hangs off the pin 6 copy, so the input is modelled as $FLIPIN and the regenerated copy keeps the name FLIP.
Discrepancy vs IC index: FLIPa is not a separate node: the FLIP line from 12D pin 6 T-joins the vertical labelled FLIPa 'to 9/9' and runs on to 11C. One drawn node, two printed names.
Discrepancy vs IC index: H128 DOES NOT GO STRAIGHT TO THE ADDER: 14B pin 8 runs through 13C(9,10->8), 13D(12,13->11) and 13C(12,13->11) before reaching 12B B4, combining with the inverted H256 and inverted FLIP. Wiring 14B pin 8 directly to 12B B4 would be wrong.
Discrepancy vs IC index: 16x16 TILES ARE VISIBLE IN THE ADDER SPLIT: 12C adds the low four bits and its sums never reach the tile map - they become the within-tile pixel phase via 11C/10C/8C. 12B and 13B add bits 16-256 and produce the map column address SH16-SH256. On an 8x8 machine the map address would start at SH8; here SH8 is peeled off separately and sent to 9/9.
Discrepancy vs IC index: REGISTER MAP MATCHES MAME: 13A decodes AB0-AB3 with /CBCS into POS0-POS3. POS0 clocks the 12A low byte (3B08), POS1 clocks the 14A ninth bit (3B09), POS2/POS3 go to sheet 8/9 for the vertical pair (3B0A/3B0B).
Discrepancy vs IC index: The right-hand block is a CPU wait handshake, not scrolling: 7C plus 5C turn /SCRCS into /MRDY2 and /SCREN, timed by 8C off the buffered 6M clock.
Discrepancy vs IC index: 5C's two '32 gates are drawn as AND bodies with bubbled inputs and output - the De Morgan dual of OR. The part is printed '32 and is recorded as printed.
Discrepancy vs IC index: Unlike the 74LS257 trap on the sister project, the '283 pin conventions here match the datasheet exactly (A1=5 A2=3 A3=14 A4=12, B1=6 B2=2 B3=15 B4=11, S1=4 S2=1 S3=13 S4=10, C0=7 C4=9).
Extraction uncertainty: 12D drawn in three places (H256 inverter pins 1-2; FLIP inverter pins 3-4 whose triangle is faint, boxed around its 3/04/12D/4 annotation cluster; buffer inverter pins 5-6) - one box per drawn section
Extraction uncertainty: 14B and 14C are each drawn as a single XOR symbol standing for all four gates, with the pin-number columns above and below; 13C and 11C are drawn gate by gate and get one box per gate
Extraction uncertainty: 7C boxes include the floating 74 part-number annotation left of each flip-flop
