Click a net label to trace it — endpoints colour-coded input · output · in/out — click an IC box (either panel) to select it in both, click again to deselect (multi-select OK), Esc clears all. Use the IC rail on the far left to jump straight to a chip. A net name shown muted like this and prefixed $ is ours - a node the 1985 drawing leaves unlabelled; every other name was read off the drawing. Hover a pin for its net's story.
Notes and open questions on this sheet (18)
Not yet walked against a physical board. The 288 pins and 76 nets on this sheet were read from the original drawing and cross-checked against MAME; every IC is still marked auto. Part numbers and pin assignments are what the drawing shows, not what has been metered.
Extraction uncertainty: FLIPa / SHFLIPa: the suffix is a small filled blob at 400 DPI - could be 'a' or Greek alpha.
Extraction uncertainty: 5D's lower gate: the pin number on the SHFLIPa input reads as a single stroke, taken as 1.
Extraction uncertainty: 3F pin 11 reads as two narrow adjacent strokes; 11 is what the datasheet requires and is consistent with the other five circled numbers.
Extraction uncertainty: The CN-2 destination of SCRY reads D1 (closed loop with a straight left side, so D not 0).
Extraction uncertainty: '5B x 4' - the second glyph is B not 8. No part number is printed for 5B; 74LS86 is taken from the XOR symbols.
Extraction uncertainty: 27128 pin 8, the '194 QC/QB outputs and the '157 fourth channel are simply not drawn; recorded as absent rather than guessed.
Discrepancy vs IC index: THE 16x16 TILE IS VISIBLE IN THE ADDRESSING. Five low address bits reach the ROMs where Commando used three: A0-A3 are V1S/V2S/V4S/V8S each XORed with SVFLIP (four row bits, sixteen rows) and A4 is SH8 XOR SHFLIP, picking which 8-pixel half of the 16-pixel row is being fetched. MAME's tilelayout confirms it byte for byte: 32*8 char increment, y-offsets 0*8..15*8, x-offsets 0..7 then 16*8+0..16*8+7 - that +16 byte step IS A4 = SH8.
Discrepancy vs IC index: THE MIRRORING LOGIC CROSS-CHECKS ITSELF: $SCRFLIP drives both the '194 shift direction (through the two 5C ORs) and the '157 SEL. High means shift right and take the QD end; low means shift left and take the QA end. The two halves agree, which is a good independent check on the routing trace.
Discrepancy vs IC index: THE '157 IS NOT REVERSED HERE. Unlike Commando's '257, this sheet numbers its own channels the datasheet way (1A = pin 2). Do not 'fix' it later.
Discrepancy vs IC index: UNRESOLVED: pin 27 (A14/PGM) is labelled on all six ROMs with NO wire drawn, while J7 is labelled '256'. The AS9 stub heading toward that row was thresholded and there is genuinely no line there. Recorded rather than invented. The likely intent is that a 27256 in the 3x socket takes AS9 as its A14 with the 1x sockets left empty.
Discrepancy vs IC index: 13D is drawn De Morgan (OR body, bubbles on both inputs and the output) but printed '08. The function is AND, as printed.
Discrepancy vs IC index: Each ROM pair is drawn as two overlapping rectangles under one '27128 x 2' caption. Every address and data wire is drawn only into the lower-left box and re-emerges from its right edge; the upper-right box shares them implicitly. Only /CE differs between the two.
Discrepancy vs IC index: Power is drawn once for all six ROMs, on the 3E/1E group at the right.
Extraction uncertainty: 1B/1C/1E are boxed on the VISIBLE drawn sliver of the rear rectangle only (top edge + left edge + '1B' designator + its own /CE and A14/PGM pins). The rear package's lower body is not drawn - it is hidden behind the front rectangle - so no ink exists there to box.
Extraction uncertainty: 3B/3C/3E are 28.2% of page HEIGHT. That is above the 25% guide but is one single drawn rectangle (a DIP28 ROM symbol), not a union.
Extraction uncertainty: 3F is 12.6% of page WIDTH, marginally over the 12% guide; it is one single drawn '157 outline.
BOARD FACT, read from the physical board by Robert - and note the board's own ROM positions are NOT the schematic's designators on this bootleg: tiles 3A, 3B, 3C = 27256, stickers 6, 7, 8 (1A, 1B, 1C empty) sprites 1L, 1N = 27128, stickers 9, 10 sprites 4L, 4N = 27256, stickers 19, 20 (3L, 3N empty) Capcom's drawing places the tile ROMs at 1B/1C/1E + 3B/3C/3E and the sprite ROMs at 1L/2L/3L + 1N/2N/3N, so the physical layout has been rearranged. Capacity still reconciles exactly: 3 x 32K tiles = 96K, and 2 x 32K + 2 x 16K sprites = 96K, matching the 6 x 16K each that the drawing spreads over twice as many packages.
